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Searched refs:offcore (Results 1 – 3 of 3) sorted by relevance

/titanic_44/usr/src/data/perfmon/
H A Dmapfile.csv10 GenuineIntel-6-37,V14,/SLM/Silvermont_matrix_V14.json,offcore
12 GenuineIntel-6-4D,V14,/SLM/Silvermont_matrix_V14.json,offcore
14 GenuineIntel-6-4C,V14,/SLM/Silvermont_matrix_V14.json,offcore
16 GenuineIntel-6-5C,V13,/GLM/goldmont_matrix_v13.json,offcore
18 GenuineIntel-6-5F,V13,/GLM/goldmont_matrix_v13.json,offcore
25 GenuineIntel-6-2A,V16,/SNB/sandybridge_matrix_v16.json,offcore
28 GenuineIntel-6-2D,V20,/JKT/Jaketown_matrix_V20.json,offcore
31 GenuineIntel-6-3A,V21,/IVB/ivybridge_matrix_v21.json,offcore
34 GenuineIntel-6-3E,V20,/IVT/ivytown_matrix_v20.json,offcore
39 GenuineIntel-6-3C,V28,/HSW/haswell_matrix_v28.json,offcore
[all …]
H A Dreadme.txt15 offcore - Contains matrix events counted from the core, but measuring responses that come from offc…
18 <microarchitecture-codename>_<core/offcore>_<version>
118 0x1A6/0x1A7: MSR_OFFCORE_RSP_X - used to configure the offcore response events
183 ----offcore----
184 …n format. There is only 1 file for core and offcore events in this format. This field is set to 1 …
/titanic_44/usr/src/tools/cpcgen/
H A Dcpcgen.c1345 char *event, *msridx, *msrval, *taken, *offcore, *counter; in cpcgen_skip_intel_entry() local
1364 nvlist_lookup_string(nvl, "Offcore", &offcore) != 0) { in cpcgen_skip_intel_entry()
1375 strcmp(offcore, "0") != 0 || strchr(ecode, ',') != NULL || in cpcgen_skip_intel_entry()