Home
last modified time | relevance | path

Searched refs:msi_ctrl (Results 1 – 11 of 11) sorted by relevance

/titanic_44/usr/src/uts/common/io/
H A Dpci_intr_lib.c106 pci_get_msi_ctrl(dev_info_t *dip, int type, ushort_t *msi_ctrl, in pci_get_msi_ctrl() argument
109 *msi_ctrl = *caps_ptr = 0; in pci_get_msi_ctrl()
121 if ((*msi_ctrl = PCI_CAP_GET16(*h, NULL, *caps_ptr, in pci_get_msi_ctrl()
126 "caps_ptr=%x msi_ctrl=%x\n", *caps_ptr, *msi_ctrl)); in pci_get_msi_ctrl()
133 if ((*msi_ctrl = PCI_CAP_GET16(*h, NULL, *caps_ptr, in pci_get_msi_ctrl()
138 "caps_ptr=%x msi_ctrl=%x\n", *caps_ptr, *msi_ctrl)); in pci_get_msi_ctrl()
157 ushort_t caps_ptr, msi_ctrl; in pci_msi_get_cap() local
165 if (pci_get_msi_ctrl(rdip, type, &msi_ctrl, in pci_msi_get_cap()
170 if (msi_ctrl & PCI_MSI_64BIT_MASK) in pci_msi_get_cap()
172 if (msi_ctrl & PCI_MSI_PVM_MASK) in pci_msi_get_cap()
[all …]
/titanic_44/usr/src/uts/i86xpv/io/psm/
H A Dxpv_intr.c242 ushort_t msi_ctrl; in apic_pci_msi_enable_vector() local
266 msi_ctrl = pci_config_get16(handle, cap_ptr + PCI_MSI_CTRL); in apic_pci_msi_enable_vector()
269 msi_ctrl |= ((highbit(count) -1) << PCI_MSI_MME_SHIFT); in apic_pci_msi_enable_vector()
270 pci_config_put16(handle, cap_ptr + PCI_MSI_CTRL, msi_ctrl); in apic_pci_msi_enable_vector()
281 ushort_t msi_ctrl; in apic_pci_msi_disable_mode() local
288 msi_ctrl = pci_config_get16(handle, cap_ptr + PCI_MSI_CTRL); in apic_pci_msi_disable_mode()
289 if (!(msi_ctrl & PCI_MSI_ENABLE_BIT)) in apic_pci_msi_disable_mode()
292 msi_ctrl &= ~PCI_MSI_ENABLE_BIT; /* MSI disable */ in apic_pci_msi_disable_mode()
293 pci_config_put16(handle, cap_ptr + PCI_MSI_CTRL, msi_ctrl); in apic_pci_msi_disable_mode()
296 msi_ctrl = pci_config_get16(handle, cap_ptr + PCI_MSIX_CTRL); in apic_pci_msi_disable_mode()
[all …]
H A Dxpv_psm.c1109 ushort_t msi_ctrl; in xpv_psm_get_msi_vector() local
1114 msi_ctrl = pci_config_get16(handle, cap_ptr + PCI_MSI_CTRL); in xpv_psm_get_msi_vector()
1118 if (msi_ctrl & PCI_MSI_64BIT_MASK) { in xpv_psm_get_msi_vector()
/titanic_44/usr/src/uts/i86pc/io/pcplusmp/
H A Dapic_introp.c62 ushort_t msi_ctrl; in apic_pci_msi_enable_vector() local
106 msi_ctrl = pci_config_get16(handle, cap_ptr + PCI_MSI_CTRL); in apic_pci_msi_enable_vector()
109 msi_ctrl |= ((highbit(count) -1) << PCI_MSI_MME_SHIFT); in apic_pci_msi_enable_vector()
110 pci_config_put16(handle, cap_ptr + PCI_MSI_CTRL, msi_ctrl); in apic_pci_msi_enable_vector()
118 if (msi_ctrl & PCI_MSI_64BIT_MASK) { in apic_pci_msi_enable_vector()
412 ushort_t msi_ctrl; in apic_pci_msi_enable_mode() local
419 msi_ctrl = pci_config_get16(handle, cap_ptr + PCI_MSI_CTRL); in apic_pci_msi_enable_mode()
420 if ((msi_ctrl & PCI_MSI_ENABLE_BIT)) in apic_pci_msi_enable_mode()
423 msi_ctrl |= PCI_MSI_ENABLE_BIT; in apic_pci_msi_enable_mode()
424 pci_config_put16(handle, cap_ptr + PCI_MSI_CTRL, msi_ctrl); in apic_pci_msi_enable_mode()
[all …]
H A Dapic_common.c1649 ushort_t msi_ctrl; in apic_pci_msi_unconfigure() local
1656 msi_ctrl = pci_config_get16(handle, cap_ptr + PCI_MSI_CTRL); in apic_pci_msi_unconfigure()
1657 msi_ctrl &= (~PCI_MSI_MME_MASK); in apic_pci_msi_unconfigure()
1658 pci_config_put16(handle, cap_ptr + PCI_MSI_CTRL, msi_ctrl); in apic_pci_msi_unconfigure()
1661 if (msi_ctrl & PCI_MSI_64BIT_MASK) { in apic_pci_msi_unconfigure()
1703 ushort_t msi_ctrl; in apic_pci_msi_disable_mode() local
1710 msi_ctrl = pci_config_get16(handle, cap_ptr + PCI_MSI_CTRL); in apic_pci_msi_disable_mode()
1711 if (!(msi_ctrl & PCI_MSI_ENABLE_BIT)) in apic_pci_msi_disable_mode()
1714 msi_ctrl &= ~PCI_MSI_ENABLE_BIT; /* MSI disable */ in apic_pci_msi_disable_mode()
1715 pci_config_put16(handle, cap_ptr + PCI_MSI_CTRL, msi_ctrl); in apic_pci_msi_disable_mode()
[all …]
/titanic_44/usr/src/uts/i86pc/io/apix/
H A Dapix_utils.c304 ushort_t msi_ctrl; in apix_pci_msi_enable_vector() local
341 msi_ctrl = pci_config_get16(handle, cap_ptr + PCI_MSI_CTRL); in apix_pci_msi_enable_vector()
344 msi_ctrl |= ((highbit(count) - 1) << PCI_MSI_MME_SHIFT); in apix_pci_msi_enable_vector()
345 pci_config_put16(handle, cap_ptr + PCI_MSI_CTRL, msi_ctrl); in apix_pci_msi_enable_vector()
348 APIX_WRITE_MSI_DATA(handle, cap_ptr, msi_ctrl, in apix_pci_msi_enable_vector()
353 if (msi_ctrl & PCI_MSI_64BIT_MASK) in apix_pci_msi_enable_vector()
357 APIX_WRITE_MSI_DATA(handle, cap_ptr, msi_ctrl, msi_data); in apix_pci_msi_enable_vector()
379 ushort_t msi_ctrl; in apix_pci_msi_enable_mode() local
386 msi_ctrl = pci_config_get16(handle, cap_ptr + PCI_MSI_CTRL); in apix_pci_msi_enable_mode()
387 if ((msi_ctrl & PCI_MSI_ENABLE_BIT)) in apix_pci_msi_enable_mode()
[all …]
H A Dapix.c1658 ushort_t msi_ctrl; in apix_grp_set_cpu() local
1715 msi_ctrl = pci_config_get16(handle, cap_ptr + PCI_MSI_CTRL); in apix_grp_set_cpu()
1718 if (msi_ctrl & PCI_MSI_PVM_MASK) { in apix_grp_set_cpu()
1719 if (msi_ctrl & PCI_MSI_64BIT_MASK) in apix_grp_set_cpu()
1734 if (msi_ctrl & PCI_MSI_PVM_MASK) { in apix_grp_set_cpu()
/titanic_44/usr/src/uts/common/os/
H A Dsunpci.c674 uint16_t msi_ctrl; local
677 msi_ctrl = pci_config_get16(confhdl, cap_ptr + PCI_MSI_CTRL);
679 if (msi_ctrl & PCI_MSI_64BIT_MASK)
682 if (msi_ctrl & PCI_MSI_PVM_MASK)
/titanic_44/usr/src/uts/common/io/ib/adapters/tavor/
H A Dtavor.c3427 ushort_t msi_ctrl = 0, caps_ctrl = 0; in tavor_intr_disable() local
3443 if ((msi_ctrl = PCI_CAP_GET16(pci_cfg_hdl, NULL, in tavor_intr_disable()
3447 ASSERT(msi_ctrl != 0); in tavor_intr_disable()
3449 if (!(msi_ctrl & PCI_MSI_ENABLE_BIT)) in tavor_intr_disable()
3452 if (msi_ctrl & PCI_MSI_PVM_MASK) { in tavor_intr_disable()
3453 int offset = (msi_ctrl & PCI_MSI_64BIT_MASK) ? in tavor_intr_disable()
3462 msi_ctrl &= ~PCI_MSI_ENABLE_BIT; in tavor_intr_disable()
3464 msi_ctrl); in tavor_intr_disable()
/titanic_44/usr/src/uts/common/io/myri10ge/drv/
H A Dmyri10ge_var.h140 uint16_t msi_ctrl; member
H A Dmyri10ge.c5669 mgp->pci_saved_state.msi_ctrl = in myri10ge_save_msi_state()
5697 mgp->pci_saved_state.msi_ctrl); in myri10ge_restore_msi_state()