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Searched refs:mask1 (Results 1 – 13 of 13) sorted by relevance

/titanic_44/usr/src/cmd/vi/port/
H A Dprintf.c77 int length,mask1,nbits,n; in viprintf() local
208 mask1 = 0x7; in viprintf()
213 mask1 = 0xf; in viprintf()
221 if (((int) num & mask1) < 10) in viprintf()
222 *--bptr = ((int) num & mask1) + 060; in viprintf()
224 *--bptr = ((int) num & mask1) + 0127; in viprintf()
/titanic_44/usr/src/lib/libast/common/string/
H A Dmodelib.h45 int mask1; /* first mask */ member
H A Dfmtmode.c44 *s++ = p->name[((mode & p->mask1) >> p->shift1) | ((mode & p->mask2) >> p->shift2)]; in fmtmode()
H A Dstrmode.c47 mode |= (p->mask1 & (c << p->shift1)) | (p->mask2 & (c << p->shift2)); in strmode()
/titanic_44/usr/src/cmd/perl/contrib/Sun/Solaris/BSM/
H A D_BSMparse.pm376 my ($mask1, $class) = split(/:/); # third field not used
377 my $mask2 = hex($mask1); # integer
/titanic_44/usr/src/uts/common/io/hxge/
H A Dhpi_pfc.c97 WRITE_TCAM_REG_MASK1(handle, tcam_ptr->mask1); in hpi_pfc_tcam_entry_read()
622 WRITE_TCAM_REG_MASK1(handle, tcam_ptr->mask1); in hpi_pfc_tcam_entry_write()
630 tcam_ptr->mask0, tcam_ptr->mask1)); in hpi_pfc_tcam_entry_write()
H A Dhxge_pfc.h233 #define mask1 mask.regs.reg1 macro
H A Dhxge_pfc.c96 tcam_rdptr.mask0, tcam_rdptr.mask1, asc_ram)); in hxge_tcam_dump_entry()
/titanic_44/usr/src/uts/common/io/nxge/npi/
H A Dnpi_fflp.c351 WRITE_TCAM_REG_MASK1(handle, tcam_ptr->mask1); in npi_fflp_tcam_entry_match()
420 READ_TCAM_REG_MASK1(handle, &tcam_ptr->mask1); in npi_fflp_tcam_entry_read()
458 WRITE_TCAM_REG_MASK1(handle, tcam_ptr->mask1); in npi_fflp_tcam_entry_write()
473 tcam_ptr->mask0, tcam_ptr->mask1, in npi_fflp_tcam_entry_write()
/titanic_44/usr/src/uts/common/io/cxgbe/common/
H A Dcommon.h435 u64 mask0, u64 mask1, unsigned int crc, bool enable);
H A Dt4_hw.c3646 u64 mask0, u64 mask1, unsigned int crc, bool enable) in t4_wol_pat_enable() argument
3661 t4_write_reg(adap, EPIO_REG(DATA2), mask1); in t4_wol_pat_enable()
3662 t4_write_reg(adap, EPIO_REG(DATA3), mask1 >> 32); in t4_wol_pat_enable()
/titanic_44/usr/src/uts/common/sys/nxge/
H A Dnxge_fflp_hw.h1268 #define mask1 mask.regs_e.reg1 macro
/titanic_44/usr/src/uts/common/io/nxge/
H A Dnxge_fflp.c115 tcam_rdptr.mask0, tcam_rdptr.mask1, in nxge_tcam_dump_entry()