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Searched refs:mask0 (Results 1 – 8 of 8) sorted by relevance

/titanic_44/usr/src/uts/common/io/hxge/
H A Dhpi_pfc.c96 WRITE_TCAM_REG_MASK0(handle, tcam_ptr->mask0); in hpi_pfc_tcam_entry_read()
621 WRITE_TCAM_REG_MASK0(handle, tcam_ptr->mask0); in hpi_pfc_tcam_entry_write()
630 tcam_ptr->mask0, tcam_ptr->mask1)); in hpi_pfc_tcam_entry_write()
H A Dhxge_pfc.h232 #define mask0 mask.regs.reg0 macro
H A Dhxge_pfc.c96 tcam_rdptr.mask0, tcam_rdptr.mask1, asc_ram)); in hxge_tcam_dump_entry()
/titanic_44/usr/src/uts/common/io/nxge/npi/
H A Dnpi_fflp.c350 WRITE_TCAM_REG_MASK0(handle, tcam_ptr->mask0); in npi_fflp_tcam_entry_match()
419 READ_TCAM_REG_MASK0(handle, &tcam_ptr->mask0); in npi_fflp_tcam_entry_read()
457 WRITE_TCAM_REG_MASK0(handle, tcam_ptr->mask0); in npi_fflp_tcam_entry_write()
473 tcam_ptr->mask0, tcam_ptr->mask1, in npi_fflp_tcam_entry_write()
/titanic_44/usr/src/uts/common/io/cxgbe/common/
H A Dcommon.h435 u64 mask0, u64 mask1, unsigned int crc, bool enable);
H A Dt4_hw.c3646 u64 mask0, u64 mask1, unsigned int crc, bool enable) in t4_wol_pat_enable() argument
3660 t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32); in t4_wol_pat_enable()
3669 t4_write_reg(adap, EPIO_REG(DATA0), mask0); in t4_wol_pat_enable()
/titanic_44/usr/src/uts/common/sys/nxge/
H A Dnxge_fflp_hw.h1267 #define mask0 mask.regs_e.reg0 macro
/titanic_44/usr/src/uts/common/io/nxge/
H A Dnxge_fflp.c115 tcam_rdptr.mask0, tcam_rdptr.mask1, in nxge_tcam_dump_entry()