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Searched refs:inw (Results 1 – 25 of 35) sorted by relevance

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/titanic_44/usr/src/grub/grub-0.97/netboot/
H A D3c90x.c268 while (inw(ioaddr + regCommandIntStatus_w) & INT_CMDINPROGRESS); in a3c90x_internal_IssueCommand()
302 while((1<<15) & inw(ioaddr + regEepromCommand_0_w)); in a3c90x_internal_ReadEeprom()
306 while((1<<15) & inw(ioaddr + regEepromCommand_0_w)); in a3c90x_internal_ReadEeprom()
307 val = inw(ioaddr + regEepromData_0_w); in a3c90x_internal_ReadEeprom()
326 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
330 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
334 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
339 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
343 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
410 while (inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_CMDINPROGRESS); in a3c90x_reset()
[all …]
H A D3c595.c201 while (inw(BASE + VX_W1_FREE_TX) < len + pad + 4) { in t595_transmit()
220 while((inw(BASE + VX_STATUS) & S_COMMAND_IN_PROGRESS) != 0) in t595_transmit()
234 cst=inw(BASE + VX_STATUS); in t595_poll()
249 status = inw(BASE + VX_W1_RX_STATUS); in t595_poll()
275 status = inw(BASE + VX_W1_RX_STATUS); in t595_poll()
301 while (inw(BASE + VX_STATUS) & S_COMMAND_IN_PROGRESS); in t595_poll()
349 return (inw(BASE + VX_W0_EEPROM_DATA));
358 vx_connectors = inw(BASE + VX_W3_RESET_OPT) & 0x7f; in vxgetlink()
H A Dsundance.c324 outw(inw(BASE + MACCtrl0) | EnbFullDuplex, in check_duplex()
337 outw(inw(BASE + MACCtrl0) | duplex ? 0x20 : 0, in check_duplex()
441 (int) inw(BASE + TxStatus), (int) inl(BASE + MACCtrl0), in sundance_reset()
442 (int) inw(BASE + MACCtrl1), (int) inw(BASE + MACCtrl0))); in sundance_reset()
454 intr_status = inw(nic->ioaddr + IntrStatus); in sundance_irq()
485 intr_status = inw(nic->ioaddr + IntrStatus); in sundance_poll()
734 outw(inw(BASE + MulticastFilter1 + 2) | 0x0200, in sundance_probe()
736 outw(inw(BASE + MACCtrl0) | EnbFlowCtrl, BASE + MACCtrl0); in sundance_probe()
759 if (!(inw(ioaddr + EECtrl) & 0x8000)) { in eeprom_read()
760 return inw(ioaddr + EEData); in eeprom_read()
H A Deepro100.c346 retval = (retval << 1) | ((inw(ee_addr) & EE_DATA_READ) ? 1 : 0); in do_eeprom_cmd()
397 status = inw(ioaddr + SCBStatus); in eepro100_transmit()
403 t, s, status, inw (ioaddr + SCBCmd)); in eepro100_transmit()
432 s1 = inw (ioaddr + SCBStatus); in eepro100_transmit()
436 s2 = inw (ioaddr + SCBStatus); in eepro100_transmit()
485 status = inw(ioaddr + SCBStatus); in eepro100_poll()
558 intr_status = inw(ioaddr + SCBStatus); in eepro100_disable()
561 inw(ioaddr + SCBStatus); in eepro100_disable()
H A D3c595.h296 #define VX_BUSY_WAIT while (inw(BASE + VX_STATUS) & S_COMMAND_IN_PROGRESS)
425 #define is_eeprom_busy(b) (inw((b)+VX_W0_EEPROM_COMMAND)&EEPROM_BUSY)
H A Drtl8139.c213 fullduplex = inw(nic->ioaddr + MII_BMCR) & BMCRDuplex; in rtl8139_probe()
398 status = inw(nic->ioaddr + IntrStatus); in rtl_transmit()
436 status = inw(nic->ioaddr + IntrStatus); in rtl_poll()
495 mask = inw(nic->ioaddr + IntrMask); in rtl_irq()
H A Dpnic.c67 status = inw ( nic->ioaddr + PNIC_REG_STAT ); in pnic_command_quiet()
69 _output_length = inw ( nic->ioaddr + PNIC_REG_LEN ); in pnic_command_quiet()
H A Dpcnet32.c295 return inw(addr + PCNET32_WIO_RDP); in pcnet32_wio_read_csr()
307 return inw(addr + PCNET32_WIO_BDP); in pcnet32_wio_read_bcr()
318 return inw(addr + PCNET32_WIO_RAP); in pcnet32_wio_read_rap()
328 inw(addr + PCNET32_WIO_RESET); in pcnet32_wio_reset()
334 return (inw(addr + PCNET32_WIO_RAP) == 88); in pcnet32_wio_check()
H A Dvia-rhine.c766 ReturnMII = inw (wMIIDATA); in ReadMII()
806 ReadMIItmp = inw (wMIIDATA); in WriteMII()
895 intr_status = inw(nic->ioaddr + IntrStatus); in rhine_irq()
1183 CRbak = inw (byCR0); in rhine_reset()
1206 intr_status = inw(nic->ioaddr + IntrStatus); in rhine_poll()
H A Dtlan.c540 u16 host_int = inw(BASE + TLAN_HOST_INT); in tlan_poll()
583 printf("AC: 0x%hX\n", inw(BASE + TLAN_CH_PARM)); in tlan_poll()
584 host_int = inw(BASE + TLAN_HOST_INT); in tlan_poll()
626 u16 host_int = inw(BASE + TLAN_HOST_INT); in tlan_transmit()
692 host_int = inw(BASE + TLAN_HOST_INT); in tlan_transmit()
719 host_int = inw(BASE + TLAN_HOST_INT); in tlan_transmit()
H A Depic100.c179 *ap++ = inw(lan0 + i*4); in epic100_probe()
504 return inw(mmdata); in mii_read()
H A Dio.h204 #define inw(port) \ macro
H A Dpci_io.c40 *value = inw(0xCFC + (where&2)); in pcibios_read_config_word()
H A Dtlan.h409 return (inw((base_addr + TLAN_DIO_DATA) + (internal_addr & 0x2))); in TLan_DioRead16()
H A Dtulip.c1676 outl(0x0f370000 | inw(ioaddr + 0x80), ioaddr + 0x80); in init_media()
1682 outl(0x0f370000 | inw(ioaddr + 0x80), ioaddr + 0x80); in init_media()
1683 outl(0x11000 | inw(ioaddr + 0xa0), ioaddr + 0xa0); in init_media()
/titanic_44/usr/src/uts/i86pc/ml/
H A Damd64.il131 .inline inw,4
134 inw (%dx)
H A Dia32.il118 .inline inw,4
121 inw (%dx)
/titanic_44/usr/src/uts/intel/asm/
H A Dsunddi.h55 inw(int port) in inw() function
/titanic_44/usr/src/uts/intel/ia32/os/
H A Dddi_i86.c508 return (ddi_swap16(inw((uintptr_t)addr))); in i_ddi_io_swap_get16()
634 *h++ = ddi_swap16(inw(port)); in i_ddi_io_swap_rep_get16()
637 *h++ = ddi_swap16(inw(port)); in i_ddi_io_swap_rep_get16()
1015 val = inw((uintptr_t)addr); in i_ddi_prot_io_get16()
1060 val = ddi_swap16(inw((uintptr_t)addr)); in i_ddi_prot_io_swap_get16()
1268 if ((*h++ = inw(port)) == 0xffff) in i_ddi_prot_io_rep_get16()
1272 if ((*h++ = inw(port)) == 0xffff) in i_ddi_prot_io_rep_get16()
1400 if ((*h++ = ddi_swap16(inw(port))) == 0xffff) in i_ddi_prot_io_swap_rep_get16()
1404 if ((*h++ = ddi_swap16(inw(port))) == 0xffff) in i_ddi_prot_io_swap_rep_get16()
/titanic_44/usr/src/uts/i86pc/os/
H A Dpci_mech1.c75 val = inw(PCI_CONFDATA | (reg & 0x2)); in pci_mech1_getw()
H A Dpci_mech2.c98 val = inw(PCI_CADDR2(device, reg)); in pci_mech2_getw()
H A Dpci_mech1_amd.c123 val = inw(PCI_CONFDATA | (reg & 0x2)); in pci_mech1_amd_getw()
/titanic_44/usr/src/cmd/mdb/intel/amd64/kmdb/
H A Dkmdb_asmutil.s141 2: inw (%dx)
/titanic_44/usr/src/uts/intel/sys/
H A Darchsystm.h103 extern uint16_t inw(int port);
/titanic_44/usr/src/uts/intel/ia32/ml/
H A Dddi_i86_asm.s346 inw (%dx)
376 inw (%dx)
1069 inw (%dx)
1078 inw (%dx)
1406 inw (%dx)
1438 inw (%dx)

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