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Searched refs:imr (Results 1 – 18 of 18) sorted by relevance

/titanic_44/usr/src/uts/sun4u/sys/
H A Dupa64s.h59 #define UPA64S_IMR_TO_CPUID(imr) (((imr) & IMR_TID) >> IMR_TID_BIT) argument
60 #define UPA64S_IMR_TO_MONDO(imr) ((imr) & IMR_MONDO) argument
62 #define UPA64S_GET_MAP_REG(mondo, imr) ((mondo) | (imr) | IMR_VALID) argument
91 uint64_t *imr[UPA64S_PORTS]; /* Intr mapping reg; treat */ member
H A Dzuluvm.h99 caddr_t mmu, caddr_t imr);
H A Dzulumod.h183 volatile uint64_t *imr; /* intr mapping regs */ member
/titanic_44/usr/src/uts/sun4u/io/
H A Dupa64s.c261 if (ddi_regs_map_setup(dip, 1, (caddr_t *)&upa64s_p->imr[0], in upa64s_attach()
268 if (ddi_regs_map_setup(dip, 2, (caddr_t *)&upa64s_p->imr[1], in upa64s_attach()
651 upaport, upa64s_p->imr[upaport], HI32(imr_data), LO32(imr_data)); in upa64s_add_intr_impl()
653 ddi_put64(upa64s_p->imr_ah[upaport], upa64s_p->imr[upaport], imr_data); in upa64s_add_intr_impl()
655 imr_data = ddi_get64(upa64s_p->imr_ah[upaport], upa64s_p->imr[upaport]); in upa64s_add_intr_impl()
697 ddi_put64(upa64s_p->imr_ah[upaport], upa64s_p->imr[upaport], 0); in upa64s_remove_intr_impl()
700 tmp = ddi_get64(upa64s_p->imr_ah[upaport], upa64s_p->imr[upaport]); in upa64s_remove_intr_impl()
878 upa64s_p->imr[0]); in save_state()
880 upa64s_p->imr[1]); in save_state()
897 ddi_put64(upa64s_p->imr_ah[0], upa64s_p->imr[0], in restore_state()
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H A Dzuluvm.c738 caddr_t mmu, caddr_t imr) in zuluvm_alloc_device() argument
747 tnf_opaque, imr, imr); in zuluvm_alloc_device()
770 zdev->imr = (uint64_t *)imr; in zuluvm_alloc_device()
1336 if (zdev->imr[idx] & ZULUVM_IMR_V_MASK) in zuluvm_do_retarget()
1337 zdev->imr[idx] = ZULUVM_IMR_V_MASK | in zuluvm_do_retarget()
1340 zdev->imr[idx] = in zuluvm_do_retarget()
1385 zdev->imr[zdev->interrupts[ino].offset] &= ~ZULUVM_IMR_V_MASK; in zuluvm_rem_intr()
1410 zdev->imr[num] |= ZULUVM_IMR_V_MASK; in zuluvm_enable_intr()
1436 zdev->imr[num] &= ~ZULUVM_IMR_V_MASK; in zuluvm_disable_intr()
/titanic_44/usr/src/uts/sun4u/opl/sys/pcicmu/
H A Dpcmu_ib.h121 #define PCMU_IB_INO_INTR_ISON(imr) ((imr) >> 31) argument
123 #define PCMU_IB_IMR2MONDO(imr) ((imr) & \ argument
/titanic_44/usr/src/uts/sun4u/io/pci/
H A Dpci_cb.c194 volatile uint64_t imr; in cb_intr_dist() local
203 imr = lddphysio(mr_pa); in cb_intr_dist()
204 if (!IB_INO_INTR_ISON(imr)) in cb_intr_dist()
213 if (ib_map_reg_get_cpu(imr) == cpu_id) in cb_intr_dist()
H A Dpci_ib.c226 volatile uint64_t imr = *imr_p; in ib_intr_dist_nintr() local
229 if (!IB_INO_INTR_ISON(imr)) in ib_intr_dist_nintr()
244 *imr_p = ib_get_map_reg(IB_IMR2MONDO(imr), cpu_id); in ib_intr_dist_nintr()
245 imr = *imr_p; /* flush previous write */ in ib_intr_dist_nintr()
282 volatile uint64_t imr, *imr_p, *state_reg; in ib_intr_dist() local
306 imr = *imr_p; /* flush previous write */ in ib_intr_dist()
320 *imr_p = ib_get_map_reg(IB_IMR2MONDO(imr), cpu_id); in ib_intr_dist()
321 imr = *imr_p; /* flush previous write */ in ib_intr_dist()
/titanic_44/usr/src/uts/sun4u/sys/pci/
H A Dpci_ib.h175 #define IB_INO_INTR_ISON(imr) ((imr) >> 31) argument
176 #define IB_IMR2MONDO(imr) \ argument
177 ((imr) & (COMMON_INTR_MAP_REG_IGN | COMMON_INTR_MAP_REG_INO))
/titanic_44/usr/src/uts/sun4u/opl/io/pcicmu/
H A Dpcmu_ib.c215 volatile uint64_t imr = *imr_p; in pcmu_ib_intr_dist_nintr() local
218 if (!PCMU_IB_INO_INTR_ISON(imr)) in pcmu_ib_intr_dist_nintr()
230 *imr_p = ib_get_map_reg(PCMU_IB_IMR2MONDO(imr), cpu_id); in pcmu_ib_intr_dist_nintr()
231 imr = *imr_p; /* flush previous write */ in pcmu_ib_intr_dist_nintr()
239 volatile uint64_t imr, *imr_p, *state_reg; in pcmu_ib_intr_dist() local
250 imr = *imr_p; /* flush previous write */ in pcmu_ib_intr_dist()
281 *imr_p = ib_get_map_reg(PCMU_IB_IMR2MONDO(imr), cpu_id); in pcmu_ib_intr_dist()
282 imr = *imr_p; /* flush previous write */ in pcmu_ib_intr_dist()
H A Dpcmu_cb.c218 volatile uint64_t imr; in pcmu_cb_intr_dist() local
229 imr = lddphysio(mr_pa); in pcmu_cb_intr_dist()
230 if (!PCMU_IB_INO_INTR_ISON(imr)) in pcmu_cb_intr_dist()
/titanic_44/usr/src/uts/common/io/cpqary3/
H A Dcpqary3_talk2ctlr.c372 intr = ddi_get32(cpqary3p->imr_handle, (uint32_t *)cpqary3p->imr); in cpqary3_intr_onoff()
377 (uint32_t *)cpqary3p->imr, intr & ~(intr_mask)); in cpqary3_intr_onoff()
380 (uint32_t *)cpqary3p->imr, (intr | intr_mask)); in cpqary3_intr_onoff()
409 intr = ddi_get32(cpqary3p->imr_handle, (uint32_t *)cpqary3p->imr); in cpqary3_lockup_intr_onoff()
414 (uint32_t *)cpqary3p->imr, intr & ~(intr_lockup_mask)); in cpqary3_lockup_intr_onoff()
417 (uint32_t *)cpqary3p->imr, (intr | intr_lockup_mask)); in cpqary3_lockup_intr_onoff()
H A Dcpqary3.h356 uint32_t *imr; member
H A Dcpqary3.c963 (caddr_t *)&cpqary3p->imr, (offset_t)I2O_INT_MASK, map_len, in cpqary3_update_ctlrdetails()
/titanic_44/usr/src/grub/grub-0.97/netboot/
H A Dsis900.h25 imr=0x14, /* Interrupt Mask Register */ enumerator
H A Dsis900.c632 outl(0, ioaddr + imr); in sis900_reset()
1130 outl(0, ioaddr + imr); in sis900_transmit()
1209 outl(0, ioaddr + imr); in sis900_disable()
/titanic_44/usr/src/cmd/cmd-inet/usr.lib/mdnsd/
H A DmDNSPosix.c798 struct ip_mreq imr; in SetupSocket() local
832 imr.imr_multiaddr.s_addr = AllDNSLinkGroupv4.NotAnInteger; in SetupSocket()
833 imr.imr_interface = ((struct sockaddr_in*)intfAddr)->sin_addr; in SetupSocket()
834 err = setsockopt(*sktPtr, IPPROTO_IP, IP_ADD_MEMBERSHIP, &imr, sizeof(imr)); in SetupSocket()
/titanic_44/usr/src/uts/common/io/scsi/adapters/smrt/
H A Dsmrt_ciss.c858 uint32_t imr = smrt_get32(smrt, CISS_I2O_INTERRUPT_MASK); in smrt_intr_set() local
863 imr &= ~CISS_IMR_BIT_SIMPLE_INTR_DISABLE; in smrt_intr_set()
865 imr |= CISS_IMR_BIT_SIMPLE_INTR_DISABLE; in smrt_intr_set()
867 smrt_put32(smrt, CISS_I2O_INTERRUPT_MASK, imr); in smrt_intr_set()