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Searched refs:ih_vector (Results 1 – 25 of 28) sorted by relevance

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/titanic_44/usr/src/uts/sun4u/io/pci/
H A Dpci_intr.c466 ino = IB_MONDO_TO_INO(hdlp->ih_vector); in pci_add_intr()
476 if (hdlp->ih_vector & PCI_PULSE_INO) { in pci_add_intr()
484 hdlp->ih_vector = CB_MONDO_TO_XMONDO(cb_p, mondo); in pci_add_intr()
542 hdlp->ih_vector = CB_MONDO_TO_XMONDO(cb_p, mondo); in pci_add_intr()
545 ino_p->ino_mondo = hdlp->ih_vector; in pci_add_intr()
548 hdlp->ih_pri, hdlp->ih_vector); in pci_add_intr()
610 hdlp->ih_vector, hdlp->ih_pri); in pci_add_intr()
622 hdlp->ih_vector, hdlp->ih_pri); in pci_add_intr()
638 ino = IB_MONDO_TO_INO(hdlp->ih_vector); in pci_remove_intr()
643 if (hdlp->ih_vector & PCI_PULSE_INO) { /* pulse interrupt */ in pci_remove_intr()
[all …]
H A Dpci_ib.c868 if (hdlp->ih_vector & PCI_PULSE_INO) { in ib_update_intr_state()
878 IB_MONDO_TO_INO(hdlp->ih_vector))) == 0) { in ib_update_intr_state()
H A Dpci_pci.c691 intr = hdlp->ih_vector; in ppb_intr_ops()
697 hdlp->ih_vector = ((intr - 1 + (d % 4)) % 4 + 1); in ppb_intr_ops()
H A Ddb21554.c2180 intr = hdlp->ih_vector; in db_intr_ops()
2186 hdlp->ih_vector = ((intr - 1 + (d % 4)) % 4 + 1); in db_intr_ops()
2193 intr, d, hdlp->ih_vector); in db_intr_ops()
/titanic_44/usr/src/uts/sun4u/opl/io/pcicmu/
H A Dpcmu_intr.c181 ino = PCMU_IB_MONDO_TO_INO(hdlp->ih_vector); in pcmu_add_intr()
219 hdlp->ih_vector = mondo; in pcmu_add_intr()
222 hdlp->ih_pri, hdlp->ih_vector); in pcmu_add_intr()
259 hdlp->ih_vector, hdlp->ih_pri); in pcmu_add_intr()
270 hdlp->ih_vector, hdlp->ih_pri); in pcmu_add_intr()
285 ino = PCMU_IB_MONDO_TO_INO(hdlp->ih_vector); in pcmu_remove_intr()
314 hdlp->ih_vector = mondo; in pcmu_remove_intr()
H A Dpcmu_ib.c737 PCMU_IB_MONDO_TO_INO((int32_t)hdlp->ih_vector))) == 0) { in pcmu_ib_update_intr_state()
/titanic_44/usr/src/uts/sun4v/io/
H A Dvnex.c409 vid_p = vnex_locate_id(rdip, hdlp->ih_vector); in vnex_enable_intr()
435 vid_p = vnex_locate_id(rdip, hdlp->ih_vector); in vnex_disable_intr()
483 ino = hdlp->ih_vector; in vnex_add_intr()
491 hdlp->ih_vector = ihdl; in vnex_add_intr()
531 ino = hdlp->ih_vector; in vnex_remove_intr()
534 hdlp->ih_vector = vid_p->vid_ihdl; in vnex_remove_intr()
/titanic_44/usr/src/uts/sun4/io/px/
H A Dpx_intr.c512 ret = px_ib_get_intr_target(px_p, hdlp->ih_vector, in px_intx_ops()
520 hdlp->ih_vector, hdlp->ih_pri, PX_INTR_STATE_ENABLE, 0, 0); in px_intx_ops()
524 hdlp->ih_vector, hdlp->ih_pri, PX_INTR_STATE_DISABLE, 0, 0); in px_intx_ops()
954 ino = hdlp->ih_vector; in px_add_intx_intr()
983 hdlp->ih_vector = ino_p->ino_sysino; in px_add_intx_intr()
1022 hdlp->ih_vector = ino_p->ino_sysino; in px_add_intx_intr()
1025 hdlp->ih_pri, hdlp->ih_vector); in px_add_intx_intr()
1108 ino = hdlp->ih_vector; in px_rem_intx_intr()
1130 hdlp->ih_vector = ino_p->ino_sysino; in px_rem_intx_intr()
1208 hdlp->ih_vector = ino_p->ino_sysino; in px_add_msiq_intr()
[all …]
/titanic_44/usr/src/uts/sun4v/io/niumx/
H A Dniumx.c886 ret = niumx_get_intr_target(niumxds_p, hdlp->ih_vector, in niumx_intr_ops()
897 ret = niumx_set_intr_target(niumxds_p, hdlp->ih_vector, in niumx_intr_ops()
926 ih_p = niumxds_p->niumx_ihtable + hdlp->ih_vector; in niumx_set_intr()
1064 ih_p = niumxds_p->niumx_ihtable + hdlp->ih_vector; in niumx_add_intr()
1067 hdlp->ih_vector, &sysino)) != H_EOK) { in niumx_add_intr()
1091 hdlp->ih_vector, ih_p->ih_inum, ih_p->ih_sysino); in niumx_add_intr()
1094 hdlp->ih_vector = ih_p->ih_sysino; in niumx_add_intr()
1149 ih_p = niumxds_p->niumx_ihtable + hdlp->ih_vector; in niumx_rem_intr()
1172 hdlp->ih_vector = (uint32_t)sysino; in niumx_rem_intr()
1173 if (hdlp->ih_vector != NULL) i_ddi_rem_ivintr(hdlp); in niumx_rem_intr()
/titanic_44/usr/src/uts/common/xen/io/
H A Dxpvd.c578 hdlp->ih_vector)); in xpvd_intr_ops()
586 hdlp->ih_vector)); in xpvd_intr_ops()
604 ec_disable_irq(hdlp->ih_vector); in xpvd_intr_ops()
606 ec_enable_irq(hdlp->ih_vector); in xpvd_intr_ops()
616 *(int *)result = ec_pending_irq(hdlp->ih_vector); in xpvd_intr_ops()
661 hdlp->ih_vector = (ushort_t)vector; in xpvd_enable_intr()
/titanic_44/usr/src/uts/i86pc/io/pcplusmp/
H A Dapic_introp.c907 if (hdlp->ih_vector > APIC_MAX_VECTOR) { in apic_intr_ops()
910 hdlp->ih_vector)); in apic_intr_ops()
915 hdlp->ih_vector = apic_vector_to_irq[hdlp->ih_vector]; in apic_intr_ops()
917 if (apic_set_cpu(hdlp->ih_vector, new_cpu, result) != in apic_intr_ops()
921 if (apic_grp_set_cpu(hdlp->ih_vector, new_cpu, in apic_intr_ops()
933 hdlp->ih_vector, hdlp->ih_private) != PSM_SUCCESS) in apic_intr_ops()
/titanic_44/usr/src/uts/common/sys/
H A Dddi_intr_impl.h81 uint32_t ih_vector; /* vector number */ member
375 ASSERT(hdlp->ih_vector == hdlp->ih_main->ih_vector); \
/titanic_44/usr/src/uts/sun4u/io/
H A Dmach_rootnex.c100 hdlp->ih_vector |= (UPAID_TO_IGN(portid) << 6); in rootnex_add_intr_impl()
140 mondo_vector |= (IMR_VALID | (uint64_t)hdlp->ih_vector); in rootnex_add_intr_impl()
171 hdlp->ih_vector |= (UPAID_TO_IGN(portid) << 6); in rootnex_remove_intr_impl()
H A Dupa64s.c616 (uint32_t *)&hdlp->ih_vector); in upa64s_add_intr_impl()
618 if (hdlp->ih_vector == 0) in upa64s_add_intr_impl()
623 ddi_driver_name(rdip), ddi_get_instance(rdip), hdlp->ih_vector); in upa64s_add_intr_impl()
648 imr_data = UPA64S_GET_MAP_REG(hdlp->ih_vector, imr_data); in upa64s_add_intr_impl()
681 (uint32_t *)&hdlp->ih_vector); in upa64s_remove_intr_impl()
683 if (hdlp->ih_vector == 0) in upa64s_remove_intr_impl()
688 ddi_driver_name(rdip), ddi_get_instance(rdip), hdlp->ih_vector); in upa64s_remove_intr_impl()
H A Dsysiosbus.c1710 "for device %s%d\n", hdlp->ih_vector, ddi_driver_name(rdip), in sbus_add_intr_impl()
1714 if (sbus_xlate_intrs(dip, rdip, (uint32_t *)&hdlp->ih_vector, in sbus_add_intr_impl()
1722 ino = hdlp->ih_vector & SBUS_MAX_INO; in sbus_add_intr_impl()
1749 "intr_handler 0x%p\n", hdlp->ih_vector, (void *)intr_handler)); in sbus_add_intr_impl()
1938 if (sbus_xlate_intrs(dip, rdip, (uint32_t *)&hdlp->ih_vector, in sbus_remove_intr_impl()
1945 ino = ((int32_t)hdlp->ih_vector) & SBUS_MAX_INO; in sbus_remove_intr_impl()
1983 hdlp->ih_vector, ino, (void *)sbus_arg, in sbus_remove_intr_impl()
2130 (uint32_t *)&hdlp->ih_vector, &hdlp->ih_pri, in sbus_intr_ops()
2612 if (sbus_xlate_intrs(dip, rdip, (uint32_t *)&hdlp->ih_vector, in sbus_update_intr_state()
2619 ino = ((int32_t)hdlp->ih_vector) & SBUS_MAX_INO; in sbus_update_intr_state()
/titanic_44/usr/src/uts/i86pc/io/pci/
H A Dpci_tools.c206 info_hdl.ih_vector = APIX_VIRTVECTOR(old_cpu, iset.ino); in pcitool_set_intr()
208 info_hdl.ih_vector = iset.ino; in pcitool_set_intr()
252 iset.ino = APIX_VIRTVEC_VECTOR(info_hdl.ih_vector); in pcitool_set_intr()
343 info_hdl.ih_vector = in pcitool_get_intr()
346 info_hdl.ih_vector = partial_iget.ino; in pcitool_get_intr()
373 iget->ino = info_hdl.ih_vector; in pcitool_get_intr()
H A Dpci_common.c587 "vector=0x%x\n", hdlp->ih_vector)); in pci_common_intr_ops()
596 "vector = %x\n", hdlp->ih_vector)); in pci_common_intr_ops()
743 "vector = 0x%x, cpu = 0x%x\n", hdlp->ih_vector, in pci_common_intr_ops()
757 hdlp->ih_vector = tmp_hdl.ih_vector; in pci_common_intr_ops()
759 "vector = 0x%x\n", hdlp->ih_vector)); in pci_common_intr_ops()
893 get_info_ii_hdl.ih_vector = vecirq; in pci_get_intr_from_vecirq()
953 hdlp->ih_vector = irq; in pci_enable_intr()
H A Dpci_kstats.c149 pci_ks_template.ihks_cookie.value.ui64 = ih_p->ih_vector; in pci_ih_ks_update()
/titanic_44/usr/src/uts/sun4/os/
H A Dddi_impl.c432 uint32_t *intr = &hdlp->ih_vector; in get_intr_parent()
596 cells_1275_copy(intr, &hdlp->ih_vector, new_intr_cells); in get_intr_parent()
736 if (hdlp->ih_vector == 0) in i_ddi_intr_ops()
737 hdlp->ih_vector = i_ddi_get_inum(rdip, hdlp->ih_inum); in i_ddi_intr_ops()
774 hdlp->ih_vector = 0; in i_ddi_intr_ops()
793 VERIFY(add_ivintr(hdlp->ih_vector, hdlp->ih_pri, in i_ddi_add_ivintr()
807 VERIFY(rem_ivintr(hdlp->ih_vector, hdlp->ih_pri) == 0); in i_ddi_rem_ivintr()
/titanic_44/usr/src/uts/i86xpv/io/psm/
H A Dxpv_psm.c721 *result = ec_pending_irq(hdlp->ih_vector); in xen_intr_ops()
727 ec_enable_irq(hdlp->ih_vector); in xen_intr_ops()
733 ec_disable_irq(hdlp->ih_vector); in xen_intr_ops()
756 err = ec_set_irq_priority(hdlp->ih_vector, new_priority); in xen_intr_ops()
769 hdlp->ih_vector, hdlp->ih_private) != PSM_SUCCESS) in xen_intr_ops()
/titanic_44/usr/src/uts/sparc/io/pciex/
H A Dpcieb_sparc.c102 intr = hdlp->ih_vector; in pcieb_plat_intr_ops()
109 hdlp->ih_vector = ((intr - 1 + (d % 4)) % 4 + 1); in pcieb_plat_intr_ops()
/titanic_44/usr/src/uts/i86pc/io/
H A Disa.c860 (int *)&hdlp->ih_vector) == PSM_FAILURE) in isa_intr_ops()
865 hdlp->ih_cb_func, DEVI(rdip)->devi_name, hdlp->ih_vector, in isa_intr_ops()
879 PSM_INTR_OP_XLATE_VECTOR, (int *)&hdlp->ih_vector); in isa_intr_ops()
883 hdlp->ih_cb_func, hdlp->ih_vector); in isa_intr_ops()
/titanic_44/usr/src/uts/i86pc/i86hvm/io/xpv/
H A Devtchn.c374 evtchn_callback_irq = ((ddi_intr_handle_impl_t *)*ihp)->ih_vector; in ec_init()
/titanic_44/usr/src/uts/sun4u/sunfire/io/
H A Dfhc.c1138 ino = FHC_INO(hdlp->ih_vector); in fhc_add_intr_impl()
1303 ("Mondo 0x%x mapping reg: 0x%p", hdlp->ih_vector, in fhc_add_intr_impl()
1338 ino = FHC_INO(hdlp->ih_vector); in fhc_remove_intr_impl()
1536 mondo = hdlp->ih_vector; in fhc_xlate_intrs()
1538 hdlp->ih_vector = (mondo | ign); in fhc_xlate_intrs()
/titanic_44/usr/src/uts/i86pc/io/apix/
H A Dapix.c1281 hdlp->ih_vector)); in apix_intr_ops()
1300 hdlp->ih_vector = APIX_VIRTVECTOR(newvecp->v_cpuid, in apix_intr_ops()
1475 return (apix_intx_get_vector(hdlp->ih_vector)); in apix_get_req_vector()
1477 virt_vec = (virt_vec == 0) ? hdlp->ih_vector : virt_vec; in apix_get_req_vector()

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