1 /****************************************************************************** 2 3 Copyright (c) 2013-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #ifndef _I40E_ADMINQ_CMD_H_ 36 #define _I40E_ADMINQ_CMD_H_ 37 38 /* This header file defines the i40e Admin Queue commands and is shared between 39 * i40e Firmware and Software. 40 * 41 * This file needs to comply with the Linux Kernel coding style. 42 */ 43 44 #define I40E_FW_API_VERSION_MAJOR 0x0001 45 #define I40E_FW_API_VERSION_MINOR 0x0005 46 47 struct i40e_aq_desc { 48 __le16 flags; 49 __le16 opcode; 50 __le16 datalen; 51 __le16 retval; 52 __le32 cookie_high; 53 __le32 cookie_low; 54 union { 55 struct { 56 __le32 param0; 57 __le32 param1; 58 __le32 param2; 59 __le32 param3; 60 } internal; 61 struct { 62 __le32 param0; 63 __le32 param1; 64 __le32 addr_high; 65 __le32 addr_low; 66 } external; 67 u8 raw[16]; 68 } params; 69 }; 70 71 /* Flags sub-structure 72 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 73 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 74 */ 75 76 /* command flags and offsets*/ 77 #define I40E_AQ_FLAG_DD_SHIFT 0 78 #define I40E_AQ_FLAG_CMP_SHIFT 1 79 #define I40E_AQ_FLAG_ERR_SHIFT 2 80 #define I40E_AQ_FLAG_VFE_SHIFT 3 81 #define I40E_AQ_FLAG_LB_SHIFT 9 82 #define I40E_AQ_FLAG_RD_SHIFT 10 83 #define I40E_AQ_FLAG_VFC_SHIFT 11 84 #define I40E_AQ_FLAG_BUF_SHIFT 12 85 #define I40E_AQ_FLAG_SI_SHIFT 13 86 #define I40E_AQ_FLAG_EI_SHIFT 14 87 #define I40E_AQ_FLAG_FE_SHIFT 15 88 89 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 90 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 91 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 92 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 93 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 94 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 95 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 96 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 97 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 98 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 99 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 100 101 /* error codes */ 102 enum i40e_admin_queue_err { 103 I40E_AQ_RC_OK = 0, /* success */ 104 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 105 I40E_AQ_RC_ENOENT = 2, /* No such element */ 106 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 107 I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 108 I40E_AQ_RC_EIO = 5, /* I/O error */ 109 I40E_AQ_RC_ENXIO = 6, /* No such resource */ 110 I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 111 I40E_AQ_RC_EAGAIN = 8, /* Try again */ 112 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 113 I40E_AQ_RC_EACCES = 10, /* Permission denied */ 114 I40E_AQ_RC_EFAULT = 11, /* Bad address */ 115 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 116 I40E_AQ_RC_EEXIST = 13, /* object already exists */ 117 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 118 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 119 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 120 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 121 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 122 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 123 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 124 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 125 I40E_AQ_RC_EFBIG = 22, /* File too large */ 126 }; 127 128 /* Admin Queue command opcodes */ 129 enum i40e_admin_queue_opc { 130 /* aq commands */ 131 i40e_aqc_opc_get_version = 0x0001, 132 i40e_aqc_opc_driver_version = 0x0002, 133 i40e_aqc_opc_queue_shutdown = 0x0003, 134 i40e_aqc_opc_set_pf_context = 0x0004, 135 136 /* resource ownership */ 137 i40e_aqc_opc_request_resource = 0x0008, 138 i40e_aqc_opc_release_resource = 0x0009, 139 140 i40e_aqc_opc_list_func_capabilities = 0x000A, 141 i40e_aqc_opc_list_dev_capabilities = 0x000B, 142 143 /* Proxy commands */ 144 i40e_aqc_opc_set_proxy_config = 0x0104, 145 i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105, 146 147 /* LAA */ 148 i40e_aqc_opc_mac_address_read = 0x0107, 149 i40e_aqc_opc_mac_address_write = 0x0108, 150 151 /* PXE */ 152 i40e_aqc_opc_clear_pxe_mode = 0x0110, 153 154 /* WoL commands */ 155 i40e_aqc_opc_set_wol_filter = 0x0120, 156 i40e_aqc_opc_get_wake_reason = 0x0121, 157 158 /* internal switch commands */ 159 i40e_aqc_opc_get_switch_config = 0x0200, 160 i40e_aqc_opc_add_statistics = 0x0201, 161 i40e_aqc_opc_remove_statistics = 0x0202, 162 i40e_aqc_opc_set_port_parameters = 0x0203, 163 i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 164 i40e_aqc_opc_set_switch_config = 0x0205, 165 i40e_aqc_opc_rx_ctl_reg_read = 0x0206, 166 i40e_aqc_opc_rx_ctl_reg_write = 0x0207, 167 168 i40e_aqc_opc_add_vsi = 0x0210, 169 i40e_aqc_opc_update_vsi_parameters = 0x0211, 170 i40e_aqc_opc_get_vsi_parameters = 0x0212, 171 172 i40e_aqc_opc_add_pv = 0x0220, 173 i40e_aqc_opc_update_pv_parameters = 0x0221, 174 i40e_aqc_opc_get_pv_parameters = 0x0222, 175 176 i40e_aqc_opc_add_veb = 0x0230, 177 i40e_aqc_opc_update_veb_parameters = 0x0231, 178 i40e_aqc_opc_get_veb_parameters = 0x0232, 179 180 i40e_aqc_opc_delete_element = 0x0243, 181 182 i40e_aqc_opc_add_macvlan = 0x0250, 183 i40e_aqc_opc_remove_macvlan = 0x0251, 184 i40e_aqc_opc_add_vlan = 0x0252, 185 i40e_aqc_opc_remove_vlan = 0x0253, 186 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 187 i40e_aqc_opc_add_tag = 0x0255, 188 i40e_aqc_opc_remove_tag = 0x0256, 189 i40e_aqc_opc_add_multicast_etag = 0x0257, 190 i40e_aqc_opc_remove_multicast_etag = 0x0258, 191 i40e_aqc_opc_update_tag = 0x0259, 192 i40e_aqc_opc_add_control_packet_filter = 0x025A, 193 i40e_aqc_opc_remove_control_packet_filter = 0x025B, 194 i40e_aqc_opc_add_cloud_filters = 0x025C, 195 i40e_aqc_opc_remove_cloud_filters = 0x025D, 196 i40e_aqc_opc_clear_wol_switch_filters = 0x025E, 197 198 i40e_aqc_opc_add_mirror_rule = 0x0260, 199 i40e_aqc_opc_delete_mirror_rule = 0x0261, 200 201 /* DCB commands */ 202 i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 203 i40e_aqc_opc_dcb_updated = 0x0302, 204 205 /* TX scheduler */ 206 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 207 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 208 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 209 i40e_aqc_opc_query_vsi_bw_config = 0x0408, 210 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 211 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 212 213 i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 214 i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 215 i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 216 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 217 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 218 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 219 i40e_aqc_opc_query_port_ets_config = 0x0419, 220 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 221 i40e_aqc_opc_suspend_port_tx = 0x041B, 222 i40e_aqc_opc_resume_port_tx = 0x041C, 223 i40e_aqc_opc_configure_partition_bw = 0x041D, 224 /* hmc */ 225 i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 226 i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 227 228 /* phy commands*/ 229 230 /* phy commands*/ 231 i40e_aqc_opc_get_phy_abilities = 0x0600, 232 i40e_aqc_opc_set_phy_config = 0x0601, 233 i40e_aqc_opc_set_mac_config = 0x0603, 234 i40e_aqc_opc_set_link_restart_an = 0x0605, 235 i40e_aqc_opc_get_link_status = 0x0607, 236 i40e_aqc_opc_set_phy_int_mask = 0x0613, 237 i40e_aqc_opc_get_local_advt_reg = 0x0614, 238 i40e_aqc_opc_set_local_advt_reg = 0x0615, 239 i40e_aqc_opc_get_partner_advt = 0x0616, 240 i40e_aqc_opc_set_lb_modes = 0x0618, 241 i40e_aqc_opc_get_phy_wol_caps = 0x0621, 242 i40e_aqc_opc_set_phy_debug = 0x0622, 243 i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 244 i40e_aqc_opc_run_phy_activity = 0x0626, 245 i40e_aqc_opc_set_phy_register = 0x0628, 246 i40e_aqc_opc_get_phy_register = 0x0629, 247 248 /* NVM commands */ 249 i40e_aqc_opc_nvm_read = 0x0701, 250 i40e_aqc_opc_nvm_erase = 0x0702, 251 i40e_aqc_opc_nvm_update = 0x0703, 252 i40e_aqc_opc_nvm_config_read = 0x0704, 253 i40e_aqc_opc_nvm_config_write = 0x0705, 254 i40e_aqc_opc_oem_post_update = 0x0720, 255 i40e_aqc_opc_thermal_sensor = 0x0721, 256 257 /* virtualization commands */ 258 i40e_aqc_opc_send_msg_to_pf = 0x0801, 259 i40e_aqc_opc_send_msg_to_vf = 0x0802, 260 i40e_aqc_opc_send_msg_to_peer = 0x0803, 261 262 /* alternate structure */ 263 i40e_aqc_opc_alternate_write = 0x0900, 264 i40e_aqc_opc_alternate_write_indirect = 0x0901, 265 i40e_aqc_opc_alternate_read = 0x0902, 266 i40e_aqc_opc_alternate_read_indirect = 0x0903, 267 i40e_aqc_opc_alternate_write_done = 0x0904, 268 i40e_aqc_opc_alternate_set_mode = 0x0905, 269 i40e_aqc_opc_alternate_clear_port = 0x0906, 270 271 /* LLDP commands */ 272 i40e_aqc_opc_lldp_get_mib = 0x0A00, 273 i40e_aqc_opc_lldp_update_mib = 0x0A01, 274 i40e_aqc_opc_lldp_add_tlv = 0x0A02, 275 i40e_aqc_opc_lldp_update_tlv = 0x0A03, 276 i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 277 i40e_aqc_opc_lldp_stop = 0x0A05, 278 i40e_aqc_opc_lldp_start = 0x0A06, 279 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, 280 i40e_aqc_opc_lldp_set_local_mib = 0x0A08, 281 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09, 282 283 /* Tunnel commands */ 284 i40e_aqc_opc_add_udp_tunnel = 0x0B00, 285 i40e_aqc_opc_del_udp_tunnel = 0x0B01, 286 i40e_aqc_opc_set_rss_key = 0x0B02, 287 i40e_aqc_opc_set_rss_lut = 0x0B03, 288 i40e_aqc_opc_get_rss_key = 0x0B04, 289 i40e_aqc_opc_get_rss_lut = 0x0B05, 290 291 /* Async Events */ 292 i40e_aqc_opc_event_lan_overflow = 0x1001, 293 294 /* OEM commands */ 295 i40e_aqc_opc_oem_parameter_change = 0xFE00, 296 i40e_aqc_opc_oem_device_status_change = 0xFE01, 297 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, 298 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, 299 300 /* debug commands */ 301 i40e_aqc_opc_debug_read_reg = 0xFF03, 302 i40e_aqc_opc_debug_write_reg = 0xFF04, 303 i40e_aqc_opc_debug_modify_reg = 0xFF07, 304 i40e_aqc_opc_debug_dump_internals = 0xFF08, 305 }; 306 307 /* command structures and indirect data structures */ 308 309 /* Structure naming conventions: 310 * - no suffix for direct command descriptor structures 311 * - _data for indirect sent data 312 * - _resp for indirect return data (data which is both will use _data) 313 * - _completion for direct return data 314 * - _element_ for repeated elements (may also be _data or _resp) 315 * 316 * Command structures are expected to overlay the params.raw member of the basic 317 * descriptor, and as such cannot exceed 16 bytes in length. 318 */ 319 320 /* This macro is used to generate a compilation error if a structure 321 * is not exactly the correct length. It gives a divide by zero error if the 322 * structure is not of the correct size, otherwise it creates an enum that is 323 * never used. 324 */ 325 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 326 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 327 328 /* This macro is used extensively to ensure that command structures are 16 329 * bytes in length as they have to map to the raw array of that size. 330 */ 331 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 332 333 /* internal (0x00XX) commands */ 334 335 /* Get version (direct 0x0001) */ 336 struct i40e_aqc_get_version { 337 __le32 rom_ver; 338 __le32 fw_build; 339 __le16 fw_major; 340 __le16 fw_minor; 341 __le16 api_major; 342 __le16 api_minor; 343 }; 344 345 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 346 347 /* Send driver version (indirect 0x0002) */ 348 struct i40e_aqc_driver_version { 349 u8 driver_major_ver; 350 u8 driver_minor_ver; 351 u8 driver_build_ver; 352 u8 driver_subbuild_ver; 353 u8 reserved[4]; 354 __le32 address_high; 355 __le32 address_low; 356 }; 357 358 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 359 360 /* Queue Shutdown (direct 0x0003) */ 361 struct i40e_aqc_queue_shutdown { 362 __le32 driver_unloading; 363 #define I40E_AQ_DRIVER_UNLOADING 0x1 364 u8 reserved[12]; 365 }; 366 367 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 368 369 /* Set PF context (0x0004, direct) */ 370 struct i40e_aqc_set_pf_context { 371 u8 pf_id; 372 u8 reserved[15]; 373 }; 374 375 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 376 377 /* Request resource ownership (direct 0x0008) 378 * Release resource ownership (direct 0x0009) 379 */ 380 #define I40E_AQ_RESOURCE_NVM 1 381 #define I40E_AQ_RESOURCE_SDP 2 382 #define I40E_AQ_RESOURCE_ACCESS_READ 1 383 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2 384 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 385 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 386 387 struct i40e_aqc_request_resource { 388 __le16 resource_id; 389 __le16 access_type; 390 __le32 timeout; 391 __le32 resource_number; 392 u8 reserved[4]; 393 }; 394 395 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 396 397 /* Get function capabilities (indirect 0x000A) 398 * Get device capabilities (indirect 0x000B) 399 */ 400 struct i40e_aqc_list_capabilites { 401 u8 command_flags; 402 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 403 u8 pf_index; 404 u8 reserved[2]; 405 __le32 count; 406 __le32 addr_high; 407 __le32 addr_low; 408 }; 409 410 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 411 412 struct i40e_aqc_list_capabilities_element_resp { 413 __le16 id; 414 u8 major_rev; 415 u8 minor_rev; 416 __le32 number; 417 __le32 logical_id; 418 __le32 phys_id; 419 u8 reserved[16]; 420 }; 421 422 /* list of caps */ 423 424 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 425 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002 426 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 427 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 428 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 429 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 430 #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008 431 #define I40E_AQ_CAP_ID_SRIOV 0x0012 432 #define I40E_AQ_CAP_ID_VF 0x0013 433 #define I40E_AQ_CAP_ID_VMDQ 0x0014 434 #define I40E_AQ_CAP_ID_8021QBG 0x0015 435 #define I40E_AQ_CAP_ID_8021QBR 0x0016 436 #define I40E_AQ_CAP_ID_VSI 0x0017 437 #define I40E_AQ_CAP_ID_DCB 0x0018 438 #define I40E_AQ_CAP_ID_FCOE 0x0021 439 #define I40E_AQ_CAP_ID_ISCSI 0x0022 440 #define I40E_AQ_CAP_ID_RSS 0x0040 441 #define I40E_AQ_CAP_ID_RXQ 0x0041 442 #define I40E_AQ_CAP_ID_TXQ 0x0042 443 #define I40E_AQ_CAP_ID_MSIX 0x0043 444 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044 445 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 446 #define I40E_AQ_CAP_ID_1588 0x0046 447 #define I40E_AQ_CAP_ID_IWARP 0x0051 448 #define I40E_AQ_CAP_ID_LED 0x0061 449 #define I40E_AQ_CAP_ID_SDP 0x0062 450 #define I40E_AQ_CAP_ID_MDIO 0x0063 451 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064 452 #define I40E_AQ_CAP_ID_NVM_MGMT 0x0080 453 #define I40E_AQ_CAP_ID_FLEX10 0x00F1 454 #define I40E_AQ_CAP_ID_CEM 0x00F2 455 456 /* Set CPPM Configuration (direct 0x0103) */ 457 struct i40e_aqc_cppm_configuration { 458 __le16 command_flags; 459 #define I40E_AQ_CPPM_EN_LTRC 0x0800 460 #define I40E_AQ_CPPM_EN_DMCTH 0x1000 461 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000 462 #define I40E_AQ_CPPM_EN_HPTC 0x4000 463 #define I40E_AQ_CPPM_EN_DMARC 0x8000 464 __le16 ttlx; 465 __le32 dmacr; 466 __le16 dmcth; 467 u8 hptc; 468 u8 reserved; 469 __le32 pfltrc; 470 }; 471 472 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 473 474 /* Set ARP Proxy command / response (indirect 0x0104) */ 475 struct i40e_aqc_arp_proxy_data { 476 __le16 command_flags; 477 #define I40E_AQ_ARP_INIT_IPV4 0x0800 478 #define I40E_AQ_ARP_UNSUP_CTL 0x1000 479 #define I40E_AQ_ARP_ENA 0x2000 480 #define I40E_AQ_ARP_ADD_IPV4 0x4000 481 #define I40E_AQ_ARP_DEL_IPV4 0x8000 482 __le16 table_id; 483 __le32 enabled_offloads; 484 #define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020 485 #define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800 486 __le32 ip_addr; 487 u8 mac_addr[6]; 488 u8 reserved[2]; 489 }; 490 491 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); 492 493 /* Set NS Proxy Table Entry Command (indirect 0x0105) */ 494 struct i40e_aqc_ns_proxy_data { 495 __le16 table_idx_mac_addr_0; 496 __le16 table_idx_mac_addr_1; 497 __le16 table_idx_ipv6_0; 498 __le16 table_idx_ipv6_1; 499 __le16 control; 500 #define I40E_AQ_NS_PROXY_ADD_0 0x0001 501 #define I40E_AQ_NS_PROXY_DEL_0 0x0002 502 #define I40E_AQ_NS_PROXY_ADD_1 0x0004 503 #define I40E_AQ_NS_PROXY_DEL_1 0x0008 504 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010 505 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020 506 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040 507 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080 508 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100 509 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200 510 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400 511 #define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800 512 #define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000 513 u8 mac_addr_0[6]; 514 u8 mac_addr_1[6]; 515 u8 local_mac_addr[6]; 516 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 517 u8 ipv6_addr_1[16]; 518 }; 519 520 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); 521 522 /* Manage LAA Command (0x0106) - obsolete */ 523 struct i40e_aqc_mng_laa { 524 __le16 command_flags; 525 #define I40E_AQ_LAA_FLAG_WR 0x8000 526 u8 reserved[2]; 527 __le32 sal; 528 __le16 sah; 529 u8 reserved2[6]; 530 }; 531 532 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); 533 534 /* Manage MAC Address Read Command (indirect 0x0107) */ 535 struct i40e_aqc_mac_address_read { 536 __le16 command_flags; 537 #define I40E_AQC_LAN_ADDR_VALID 0x10 538 #define I40E_AQC_SAN_ADDR_VALID 0x20 539 #define I40E_AQC_PORT_ADDR_VALID 0x40 540 #define I40E_AQC_WOL_ADDR_VALID 0x80 541 #define I40E_AQC_MC_MAG_EN_VALID 0x100 542 #define I40E_AQC_WOL_PRESERVE_STATUS 0x200 543 #define I40E_AQC_ADDR_VALID_MASK 0x3F0 544 u8 reserved[6]; 545 __le32 addr_high; 546 __le32 addr_low; 547 }; 548 549 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 550 551 struct i40e_aqc_mac_address_read_data { 552 u8 pf_lan_mac[6]; 553 u8 pf_san_mac[6]; 554 u8 port_mac[6]; 555 u8 pf_wol_mac[6]; 556 }; 557 558 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 559 560 /* Manage MAC Address Write Command (0x0108) */ 561 struct i40e_aqc_mac_address_write { 562 __le16 command_flags; 563 #define I40E_AQC_MC_MAG_EN 0x0100 564 #define I40E_AQC_WOL_PRESERVE_ON_PFR 0x0200 565 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 566 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 567 #define I40E_AQC_WRITE_TYPE_PORT 0x8000 568 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 569 #define I40E_AQC_WRITE_TYPE_MASK 0xC000 570 571 __le16 mac_sah; 572 __le32 mac_sal; 573 u8 reserved[8]; 574 }; 575 576 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 577 578 /* PXE commands (0x011x) */ 579 580 /* Clear PXE Command and response (direct 0x0110) */ 581 struct i40e_aqc_clear_pxe { 582 u8 rx_cnt; 583 u8 reserved[15]; 584 }; 585 586 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 587 588 /* Set WoL Filter (0x0120) */ 589 590 struct i40e_aqc_set_wol_filter { 591 __le16 filter_index; 592 #define I40E_AQC_MAX_NUM_WOL_FILTERS 8 593 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15 594 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \ 595 I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT) 596 597 #define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0 598 #define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \ 599 I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT) 600 __le16 cmd_flags; 601 #define I40E_AQC_SET_WOL_FILTER 0x8000 602 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000 603 #define I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR 0x2000 604 #define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0 605 #define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1 606 __le16 valid_flags; 607 #define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000 608 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000 609 u8 reserved[2]; 610 __le32 address_high; 611 __le32 address_low; 612 }; 613 614 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter); 615 616 struct i40e_aqc_set_wol_filter_data { 617 u8 filter[128]; 618 u8 mask[16]; 619 }; 620 621 I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data); 622 623 /* Get Wake Reason (0x0121) */ 624 625 struct i40e_aqc_get_wake_reason_completion { 626 u8 reserved_1[2]; 627 __le16 wake_reason; 628 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0 629 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \ 630 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT) 631 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8 632 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \ 633 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT) 634 u8 reserved_2[12]; 635 }; 636 637 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion); 638 639 /* Switch configuration commands (0x02xx) */ 640 641 /* Used by many indirect commands that only pass an seid and a buffer in the 642 * command 643 */ 644 struct i40e_aqc_switch_seid { 645 __le16 seid; 646 u8 reserved[6]; 647 __le32 addr_high; 648 __le32 addr_low; 649 }; 650 651 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 652 653 /* Get Switch Configuration command (indirect 0x0200) 654 * uses i40e_aqc_switch_seid for the descriptor 655 */ 656 struct i40e_aqc_get_switch_config_header_resp { 657 __le16 num_reported; 658 __le16 num_total; 659 u8 reserved[12]; 660 }; 661 662 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); 663 664 struct i40e_aqc_switch_config_element_resp { 665 u8 element_type; 666 #define I40E_AQ_SW_ELEM_TYPE_MAC 1 667 #define I40E_AQ_SW_ELEM_TYPE_PF 2 668 #define I40E_AQ_SW_ELEM_TYPE_VF 3 669 #define I40E_AQ_SW_ELEM_TYPE_EMP 4 670 #define I40E_AQ_SW_ELEM_TYPE_BMC 5 671 #define I40E_AQ_SW_ELEM_TYPE_PV 16 672 #define I40E_AQ_SW_ELEM_TYPE_VEB 17 673 #define I40E_AQ_SW_ELEM_TYPE_PA 18 674 #define I40E_AQ_SW_ELEM_TYPE_VSI 19 675 u8 revision; 676 #define I40E_AQ_SW_ELEM_REV_1 1 677 __le16 seid; 678 __le16 uplink_seid; 679 __le16 downlink_seid; 680 u8 reserved[3]; 681 u8 connection_type; 682 #define I40E_AQ_CONN_TYPE_REGULAR 0x1 683 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2 684 #define I40E_AQ_CONN_TYPE_CASCADED 0x3 685 __le16 scheduler_id; 686 __le16 element_info; 687 }; 688 689 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); 690 691 /* Get Switch Configuration (indirect 0x0200) 692 * an array of elements are returned in the response buffer 693 * the first in the array is the header, remainder are elements 694 */ 695 struct i40e_aqc_get_switch_config_resp { 696 struct i40e_aqc_get_switch_config_header_resp header; 697 struct i40e_aqc_switch_config_element_resp element[1]; 698 }; 699 700 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); 701 702 /* Add Statistics (direct 0x0201) 703 * Remove Statistics (direct 0x0202) 704 */ 705 struct i40e_aqc_add_remove_statistics { 706 __le16 seid; 707 __le16 vlan; 708 __le16 stat_index; 709 u8 reserved[10]; 710 }; 711 712 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 713 714 /* Set Port Parameters command (direct 0x0203) */ 715 struct i40e_aqc_set_port_parameters { 716 __le16 command_flags; 717 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 718 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 719 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 720 __le16 bad_frame_vsi; 721 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0 722 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF 723 __le16 default_seid; /* reserved for command */ 724 u8 reserved[10]; 725 }; 726 727 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 728 729 /* Get Switch Resource Allocation (indirect 0x0204) */ 730 struct i40e_aqc_get_switch_resource_alloc { 731 u8 num_entries; /* reserved for command */ 732 u8 reserved[7]; 733 __le32 addr_high; 734 __le32 addr_low; 735 }; 736 737 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 738 739 /* expect an array of these structs in the response buffer */ 740 struct i40e_aqc_switch_resource_alloc_element_resp { 741 u8 resource_type; 742 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0 743 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1 744 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 745 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3 746 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 747 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 748 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 749 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 750 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 751 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 752 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 753 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 754 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 755 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 756 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 757 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 758 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 759 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 760 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 761 u8 reserved1; 762 __le16 guaranteed; 763 __le16 total; 764 __le16 used; 765 __le16 total_unalloced; 766 u8 reserved2[6]; 767 }; 768 769 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); 770 771 /* Set Switch Configuration (direct 0x0205) */ 772 struct i40e_aqc_set_switch_config { 773 __le16 flags; 774 /* flags used for both fields below */ 775 #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001 776 #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002 777 __le16 valid_flags; 778 u8 reserved[12]; 779 }; 780 781 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config); 782 783 /* Read Receive control registers (direct 0x0206) 784 * Write Receive control registers (direct 0x0207) 785 * used for accessing Rx control registers that can be 786 * slow and need special handling when under high Rx load 787 */ 788 struct i40e_aqc_rx_ctl_reg_read_write { 789 __le32 reserved1; 790 __le32 address; 791 __le32 reserved2; 792 __le32 value; 793 }; 794 795 I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write); 796 797 /* Add VSI (indirect 0x0210) 798 * this indirect command uses struct i40e_aqc_vsi_properties_data 799 * as the indirect buffer (128 bytes) 800 * 801 * Update VSI (indirect 0x211) 802 * uses the same data structure as Add VSI 803 * 804 * Get VSI (indirect 0x0212) 805 * uses the same completion and data structure as Add VSI 806 */ 807 struct i40e_aqc_add_get_update_vsi { 808 __le16 uplink_seid; 809 u8 connection_type; 810 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 811 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 812 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 813 u8 reserved1; 814 u8 vf_id; 815 u8 reserved2; 816 __le16 vsi_flags; 817 #define I40E_AQ_VSI_TYPE_SHIFT 0x0 818 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 819 #define I40E_AQ_VSI_TYPE_VF 0x0 820 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1 821 #define I40E_AQ_VSI_TYPE_PF 0x2 822 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 823 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 824 __le32 addr_high; 825 __le32 addr_low; 826 }; 827 828 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 829 830 struct i40e_aqc_add_get_update_vsi_completion { 831 __le16 seid; 832 __le16 vsi_number; 833 __le16 vsi_used; 834 __le16 vsi_free; 835 __le32 addr_high; 836 __le32 addr_low; 837 }; 838 839 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 840 841 struct i40e_aqc_vsi_properties_data { 842 /* first 96 byte are written by SW */ 843 __le16 valid_sections; 844 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 845 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 846 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 847 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 848 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 849 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 850 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 851 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 852 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 853 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 854 /* switch section */ 855 __le16 switch_id; /* 12bit id combined with flags below */ 856 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 857 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 858 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 859 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 860 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 861 u8 sw_reserved[2]; 862 /* security section */ 863 u8 sec_flags; 864 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 865 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 866 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 867 u8 sec_reserved; 868 /* VLAN section */ 869 __le16 pvid; /* VLANS include priority bits */ 870 __le16 fcoe_pvid; 871 u8 port_vlan_flags; 872 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 873 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 874 I40E_AQ_VSI_PVLAN_MODE_SHIFT) 875 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 876 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 877 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 878 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 879 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 880 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 881 I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 882 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 883 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 884 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 885 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 886 u8 pvlan_reserved[3]; 887 /* ingress egress up sections */ 888 __le32 ingress_table; /* bitmap, 3 bits per up */ 889 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 890 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 891 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 892 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 893 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 894 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 895 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 896 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 897 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 898 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 899 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 900 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 901 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 902 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 903 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 904 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 905 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 906 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 907 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 908 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 909 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 910 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 911 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 912 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 913 __le32 egress_table; /* same defines as for ingress table */ 914 /* cascaded PV section */ 915 __le16 cas_pv_tag; 916 u8 cas_pv_flags; 917 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 918 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 919 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 920 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 921 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 922 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 923 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 924 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 925 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 926 u8 cas_pv_reserved; 927 /* queue mapping section */ 928 __le16 mapping_flags; 929 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 930 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 931 __le16 queue_mapping[16]; 932 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0 933 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 934 __le16 tc_mapping[8]; 935 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 936 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 937 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 938 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 939 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 940 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 941 /* queueing option section */ 942 u8 queueing_opt_flags; 943 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04 944 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08 945 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 946 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 947 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00 948 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40 949 u8 queueing_opt_reserved[3]; 950 /* scheduler section */ 951 u8 up_enable_bits; 952 u8 sched_reserved; 953 /* outer up section */ 954 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 955 u8 cmd_reserved[8]; 956 /* last 32 bytes are written by FW */ 957 __le16 qs_handle[8]; 958 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 959 __le16 stat_counter_idx; 960 __le16 sched_id; 961 u8 resp_reserved[12]; 962 }; 963 964 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 965 966 /* Add Port Virtualizer (direct 0x0220) 967 * also used for update PV (direct 0x0221) but only flags are used 968 * (IS_CTRL_PORT only works on add PV) 969 */ 970 struct i40e_aqc_add_update_pv { 971 __le16 command_flags; 972 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1 973 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 974 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 975 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 976 __le16 uplink_seid; 977 __le16 connected_seid; 978 u8 reserved[10]; 979 }; 980 981 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 982 983 struct i40e_aqc_add_update_pv_completion { 984 /* reserved for update; for add also encodes error if rc == ENOSPC */ 985 __le16 pv_seid; 986 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 987 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 988 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 989 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 990 u8 reserved[14]; 991 }; 992 993 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 994 995 /* Get PV Params (direct 0x0222) 996 * uses i40e_aqc_switch_seid for the descriptor 997 */ 998 999 struct i40e_aqc_get_pv_params_completion { 1000 __le16 seid; 1001 __le16 default_stag; 1002 __le16 pv_flags; /* same flags as add_pv */ 1003 #define I40E_AQC_GET_PV_PV_TYPE 0x1 1004 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 1005 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 1006 u8 reserved[8]; 1007 __le16 default_port_seid; 1008 }; 1009 1010 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 1011 1012 /* Add VEB (direct 0x0230) */ 1013 struct i40e_aqc_add_veb { 1014 __le16 uplink_seid; 1015 __le16 downlink_seid; 1016 __le16 veb_flags; 1017 #define I40E_AQC_ADD_VEB_FLOATING 0x1 1018 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 1019 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 1020 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 1021 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 1022 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 1023 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */ 1024 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10 1025 u8 enable_tcs; 1026 u8 reserved[9]; 1027 }; 1028 1029 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 1030 1031 struct i40e_aqc_add_veb_completion { 1032 u8 reserved[6]; 1033 __le16 switch_seid; 1034 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 1035 __le16 veb_seid; 1036 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 1037 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 1038 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 1039 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 1040 __le16 statistic_index; 1041 __le16 vebs_used; 1042 __le16 vebs_free; 1043 }; 1044 1045 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 1046 1047 /* Get VEB Parameters (direct 0x0232) 1048 * uses i40e_aqc_switch_seid for the descriptor 1049 */ 1050 struct i40e_aqc_get_veb_parameters_completion { 1051 __le16 seid; 1052 __le16 switch_id; 1053 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 1054 __le16 statistic_index; 1055 __le16 vebs_used; 1056 __le16 vebs_free; 1057 u8 reserved[4]; 1058 }; 1059 1060 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 1061 1062 /* Delete Element (direct 0x0243) 1063 * uses the generic i40e_aqc_switch_seid 1064 */ 1065 1066 /* Add MAC-VLAN (indirect 0x0250) */ 1067 1068 /* used for the command for most vlan commands */ 1069 struct i40e_aqc_macvlan { 1070 __le16 num_addresses; 1071 __le16 seid[3]; 1072 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 1073 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 1074 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1075 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 1076 __le32 addr_high; 1077 __le32 addr_low; 1078 }; 1079 1080 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 1081 1082 /* indirect data for command and response */ 1083 struct i40e_aqc_add_macvlan_element_data { 1084 u8 mac_addr[6]; 1085 __le16 vlan_tag; 1086 __le16 flags; 1087 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 1088 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 1089 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 1090 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 1091 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010 1092 __le16 queue_number; 1093 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 1094 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 1095 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1096 /* response section */ 1097 u8 match_method; 1098 #define I40E_AQC_MM_PERFECT_MATCH 0x01 1099 #define I40E_AQC_MM_HASH_MATCH 0x02 1100 #define I40E_AQC_MM_ERR_NO_RES 0xFF 1101 u8 reserved1[3]; 1102 }; 1103 1104 struct i40e_aqc_add_remove_macvlan_completion { 1105 __le16 perfect_mac_used; 1106 __le16 perfect_mac_free; 1107 __le16 unicast_hash_free; 1108 __le16 multicast_hash_free; 1109 __le32 addr_high; 1110 __le32 addr_low; 1111 }; 1112 1113 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 1114 1115 /* Remove MAC-VLAN (indirect 0x0251) 1116 * uses i40e_aqc_macvlan for the descriptor 1117 * data points to an array of num_addresses of elements 1118 */ 1119 1120 struct i40e_aqc_remove_macvlan_element_data { 1121 u8 mac_addr[6]; 1122 __le16 vlan_tag; 1123 u8 flags; 1124 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 1125 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 1126 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 1127 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 1128 u8 reserved[3]; 1129 /* reply section */ 1130 u8 error_code; 1131 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 1132 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 1133 u8 reply_reserved[3]; 1134 }; 1135 1136 /* Add VLAN (indirect 0x0252) 1137 * Remove VLAN (indirect 0x0253) 1138 * use the generic i40e_aqc_macvlan for the command 1139 */ 1140 struct i40e_aqc_add_remove_vlan_element_data { 1141 __le16 vlan_tag; 1142 u8 vlan_flags; 1143 /* flags for add VLAN */ 1144 #define I40E_AQC_ADD_VLAN_LOCAL 0x1 1145 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1146 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1147 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1148 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1149 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1150 #define I40E_AQC_VLAN_PTYPE_SHIFT 3 1151 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1152 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1153 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1154 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1155 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1156 /* flags for remove VLAN */ 1157 #define I40E_AQC_REMOVE_VLAN_ALL 0x1 1158 u8 reserved; 1159 u8 result; 1160 /* flags for add VLAN */ 1161 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1162 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1163 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1164 /* flags for remove VLAN */ 1165 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1166 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1167 u8 reserved1[3]; 1168 }; 1169 1170 struct i40e_aqc_add_remove_vlan_completion { 1171 u8 reserved[4]; 1172 __le16 vlans_used; 1173 __le16 vlans_free; 1174 __le32 addr_high; 1175 __le32 addr_low; 1176 }; 1177 1178 /* Set VSI Promiscuous Modes (direct 0x0254) */ 1179 struct i40e_aqc_set_vsi_promiscuous_modes { 1180 __le16 promiscuous_flags; 1181 __le16 valid_flags; 1182 /* flags used for both fields above */ 1183 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1184 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1185 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1186 #define I40E_AQC_SET_VSI_DEFAULT 0x08 1187 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1188 #define I40E_AQC_SET_VSI_PROMISC_TX 0x8000 1189 __le16 seid; 1190 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1191 __le16 vlan_tag; 1192 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF 1193 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1194 u8 reserved[8]; 1195 }; 1196 1197 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1198 1199 /* Add S/E-tag command (direct 0x0255) 1200 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1201 */ 1202 struct i40e_aqc_add_tag { 1203 __le16 flags; 1204 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1205 __le16 seid; 1206 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1207 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1208 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1209 __le16 tag; 1210 __le16 queue_number; 1211 u8 reserved[8]; 1212 }; 1213 1214 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1215 1216 struct i40e_aqc_add_remove_tag_completion { 1217 u8 reserved[12]; 1218 __le16 tags_used; 1219 __le16 tags_free; 1220 }; 1221 1222 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1223 1224 /* Remove S/E-tag command (direct 0x0256) 1225 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1226 */ 1227 struct i40e_aqc_remove_tag { 1228 __le16 seid; 1229 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1230 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1231 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1232 __le16 tag; 1233 u8 reserved[12]; 1234 }; 1235 1236 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); 1237 1238 /* Add multicast E-Tag (direct 0x0257) 1239 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1240 * and no external data 1241 */ 1242 struct i40e_aqc_add_remove_mcast_etag { 1243 __le16 pv_seid; 1244 __le16 etag; 1245 u8 num_unicast_etags; 1246 u8 reserved[3]; 1247 __le32 addr_high; /* address of array of 2-byte s-tags */ 1248 __le32 addr_low; 1249 }; 1250 1251 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1252 1253 struct i40e_aqc_add_remove_mcast_etag_completion { 1254 u8 reserved[4]; 1255 __le16 mcast_etags_used; 1256 __le16 mcast_etags_free; 1257 __le32 addr_high; 1258 __le32 addr_low; 1259 1260 }; 1261 1262 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1263 1264 /* Update S/E-Tag (direct 0x0259) */ 1265 struct i40e_aqc_update_tag { 1266 __le16 seid; 1267 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1268 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1269 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1270 __le16 old_tag; 1271 __le16 new_tag; 1272 u8 reserved[10]; 1273 }; 1274 1275 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1276 1277 struct i40e_aqc_update_tag_completion { 1278 u8 reserved[12]; 1279 __le16 tags_used; 1280 __le16 tags_free; 1281 }; 1282 1283 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1284 1285 /* Add Control Packet filter (direct 0x025A) 1286 * Remove Control Packet filter (direct 0x025B) 1287 * uses the i40e_aqc_add_oveb_cloud, 1288 * and the generic direct completion structure 1289 */ 1290 struct i40e_aqc_add_remove_control_packet_filter { 1291 u8 mac[6]; 1292 __le16 etype; 1293 __le16 flags; 1294 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1295 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1296 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1297 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1298 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1299 __le16 seid; 1300 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1301 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1302 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1303 __le16 queue; 1304 u8 reserved[2]; 1305 }; 1306 1307 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1308 1309 struct i40e_aqc_add_remove_control_packet_filter_completion { 1310 __le16 mac_etype_used; 1311 __le16 etype_used; 1312 __le16 mac_etype_free; 1313 __le16 etype_free; 1314 u8 reserved[8]; 1315 }; 1316 1317 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1318 1319 /* Add Cloud filters (indirect 0x025C) 1320 * Remove Cloud filters (indirect 0x025D) 1321 * uses the i40e_aqc_add_remove_cloud_filters, 1322 * and the generic indirect completion structure 1323 */ 1324 struct i40e_aqc_add_remove_cloud_filters { 1325 u8 num_filters; 1326 u8 reserved; 1327 __le16 seid; 1328 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1329 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1330 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1331 u8 reserved2[4]; 1332 __le32 addr_high; 1333 __le32 addr_low; 1334 }; 1335 1336 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1337 1338 struct i40e_aqc_add_remove_cloud_filters_element_data { 1339 u8 outer_mac[6]; 1340 u8 inner_mac[6]; 1341 __le16 inner_vlan; 1342 union { 1343 struct { 1344 u8 reserved[12]; 1345 u8 data[4]; 1346 } v4; 1347 struct { 1348 u8 data[16]; 1349 } v6; 1350 } ipaddr; 1351 __le16 flags; 1352 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1353 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1354 I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1355 /* 0x0000 reserved */ 1356 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 1357 /* 0x0002 reserved */ 1358 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1359 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1360 /* 0x0005 reserved */ 1361 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1362 /* 0x0007 reserved */ 1363 /* 0x0008 reserved */ 1364 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1365 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1366 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1367 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1368 1369 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1370 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1371 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1372 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1373 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1374 1375 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1376 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1377 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0 1378 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1379 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2 1380 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1381 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4 1382 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5 1383 1384 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000 1385 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000 1386 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000 1387 1388 __le32 tenant_id; 1389 u8 reserved[4]; 1390 __le16 queue_number; 1391 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1392 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ 1393 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1394 u8 reserved2[14]; 1395 /* response section */ 1396 u8 allocation_result; 1397 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1398 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1399 u8 response_reserved[7]; 1400 }; 1401 1402 struct i40e_aqc_remove_cloud_filters_completion { 1403 __le16 perfect_ovlan_used; 1404 __le16 perfect_ovlan_free; 1405 __le16 vlan_used; 1406 __le16 vlan_free; 1407 __le32 addr_high; 1408 __le32 addr_low; 1409 }; 1410 1411 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1412 1413 /* Add Mirror Rule (indirect or direct 0x0260) 1414 * Delete Mirror Rule (indirect or direct 0x0261) 1415 * note: some rule types (4,5) do not use an external buffer. 1416 * take care to set the flags correctly. 1417 */ 1418 struct i40e_aqc_add_delete_mirror_rule { 1419 __le16 seid; 1420 __le16 rule_type; 1421 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1422 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1423 I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1424 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1425 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1426 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1427 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1428 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1429 __le16 num_entries; 1430 __le16 destination; /* VSI for add, rule id for delete */ 1431 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1432 __le32 addr_low; 1433 }; 1434 1435 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1436 1437 struct i40e_aqc_add_delete_mirror_rule_completion { 1438 u8 reserved[2]; 1439 __le16 rule_id; /* only used on add */ 1440 __le16 mirror_rules_used; 1441 __le16 mirror_rules_free; 1442 __le32 addr_high; 1443 __le32 addr_low; 1444 }; 1445 1446 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1447 1448 /* DCB 0x03xx*/ 1449 1450 /* PFC Ignore (direct 0x0301) 1451 * the command and response use the same descriptor structure 1452 */ 1453 struct i40e_aqc_pfc_ignore { 1454 u8 tc_bitmap; 1455 u8 command_flags; /* unused on response */ 1456 #define I40E_AQC_PFC_IGNORE_SET 0x80 1457 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1458 u8 reserved[14]; 1459 }; 1460 1461 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1462 1463 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1464 * with no parameters 1465 */ 1466 1467 /* TX scheduler 0x04xx */ 1468 1469 /* Almost all the indirect commands use 1470 * this generic struct to pass the SEID in param0 1471 */ 1472 struct i40e_aqc_tx_sched_ind { 1473 __le16 vsi_seid; 1474 u8 reserved[6]; 1475 __le32 addr_high; 1476 __le32 addr_low; 1477 }; 1478 1479 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1480 1481 /* Several commands respond with a set of queue set handles */ 1482 struct i40e_aqc_qs_handles_resp { 1483 __le16 qs_handles[8]; 1484 }; 1485 1486 /* Configure VSI BW limits (direct 0x0400) */ 1487 struct i40e_aqc_configure_vsi_bw_limit { 1488 __le16 vsi_seid; 1489 u8 reserved[2]; 1490 __le16 credit; 1491 u8 reserved1[2]; 1492 u8 max_credit; /* 0-3, limit = 2^max */ 1493 u8 reserved2[7]; 1494 }; 1495 1496 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1497 1498 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1499 * responds with i40e_aqc_qs_handles_resp 1500 */ 1501 struct i40e_aqc_configure_vsi_ets_sla_bw_data { 1502 u8 tc_valid_bits; 1503 u8 reserved[15]; 1504 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1505 1506 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1507 __le16 tc_bw_max[2]; 1508 u8 reserved1[28]; 1509 }; 1510 1511 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); 1512 1513 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1514 * responds with i40e_aqc_qs_handles_resp 1515 */ 1516 struct i40e_aqc_configure_vsi_tc_bw_data { 1517 u8 tc_valid_bits; 1518 u8 reserved[3]; 1519 u8 tc_bw_credits[8]; 1520 u8 reserved1[4]; 1521 __le16 qs_handles[8]; 1522 }; 1523 1524 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); 1525 1526 /* Query vsi bw configuration (indirect 0x0408) */ 1527 struct i40e_aqc_query_vsi_bw_config_resp { 1528 u8 tc_valid_bits; 1529 u8 tc_suspended_bits; 1530 u8 reserved[14]; 1531 __le16 qs_handles[8]; 1532 u8 reserved1[4]; 1533 __le16 port_bw_limit; 1534 u8 reserved2[2]; 1535 u8 max_bw; /* 0-3, limit = 2^max */ 1536 u8 reserved3[23]; 1537 }; 1538 1539 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); 1540 1541 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1542 struct i40e_aqc_query_vsi_ets_sla_config_resp { 1543 u8 tc_valid_bits; 1544 u8 reserved[3]; 1545 u8 share_credits[8]; 1546 __le16 credits[8]; 1547 1548 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1549 __le16 tc_bw_max[2]; 1550 }; 1551 1552 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); 1553 1554 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1555 struct i40e_aqc_configure_switching_comp_bw_limit { 1556 __le16 seid; 1557 u8 reserved[2]; 1558 __le16 credit; 1559 u8 reserved1[2]; 1560 u8 max_bw; /* 0-3, limit = 2^max */ 1561 u8 reserved2[7]; 1562 }; 1563 1564 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1565 1566 /* Enable Physical Port ETS (indirect 0x0413) 1567 * Modify Physical Port ETS (indirect 0x0414) 1568 * Disable Physical Port ETS (indirect 0x0415) 1569 */ 1570 struct i40e_aqc_configure_switching_comp_ets_data { 1571 u8 reserved[4]; 1572 u8 tc_valid_bits; 1573 u8 seepage; 1574 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1575 u8 tc_strict_priority_flags; 1576 u8 reserved1[17]; 1577 u8 tc_bw_share_credits[8]; 1578 u8 reserved2[96]; 1579 }; 1580 1581 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); 1582 1583 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1584 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1585 u8 tc_valid_bits; 1586 u8 reserved[15]; 1587 __le16 tc_bw_credit[8]; 1588 1589 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1590 __le16 tc_bw_max[2]; 1591 u8 reserved1[28]; 1592 }; 1593 1594 I40E_CHECK_STRUCT_LEN(0x40, 1595 i40e_aqc_configure_switching_comp_ets_bw_limit_data); 1596 1597 /* Configure Switching Component Bandwidth Allocation per Tc 1598 * (indirect 0x0417) 1599 */ 1600 struct i40e_aqc_configure_switching_comp_bw_config_data { 1601 u8 tc_valid_bits; 1602 u8 reserved[2]; 1603 u8 absolute_credits; /* bool */ 1604 u8 tc_bw_share_credits[8]; 1605 u8 reserved1[20]; 1606 }; 1607 1608 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); 1609 1610 /* Query Switching Component Configuration (indirect 0x0418) */ 1611 struct i40e_aqc_query_switching_comp_ets_config_resp { 1612 u8 tc_valid_bits; 1613 u8 reserved[35]; 1614 __le16 port_bw_limit; 1615 u8 reserved1[2]; 1616 u8 tc_bw_max; /* 0-3, limit = 2^max */ 1617 u8 reserved2[23]; 1618 }; 1619 1620 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); 1621 1622 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1623 struct i40e_aqc_query_port_ets_config_resp { 1624 u8 reserved[4]; 1625 u8 tc_valid_bits; 1626 u8 reserved1; 1627 u8 tc_strict_priority_bits; 1628 u8 reserved2; 1629 u8 tc_bw_share_credits[8]; 1630 __le16 tc_bw_limits[8]; 1631 1632 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1633 __le16 tc_bw_max[2]; 1634 u8 reserved3[32]; 1635 }; 1636 1637 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); 1638 1639 /* Query Switching Component Bandwidth Allocation per Traffic Type 1640 * (indirect 0x041A) 1641 */ 1642 struct i40e_aqc_query_switching_comp_bw_config_resp { 1643 u8 tc_valid_bits; 1644 u8 reserved[2]; 1645 u8 absolute_credits_enable; /* bool */ 1646 u8 tc_bw_share_credits[8]; 1647 __le16 tc_bw_limits[8]; 1648 1649 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1650 __le16 tc_bw_max[2]; 1651 }; 1652 1653 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); 1654 1655 /* Suspend/resume port TX traffic 1656 * (direct 0x041B and 0x041C) uses the generic SEID struct 1657 */ 1658 1659 /* Configure partition BW 1660 * (indirect 0x041D) 1661 */ 1662 struct i40e_aqc_configure_partition_bw_data { 1663 __le16 pf_valid_bits; 1664 u8 min_bw[16]; /* guaranteed bandwidth */ 1665 u8 max_bw[16]; /* bandwidth limit */ 1666 }; 1667 1668 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); 1669 1670 /* Get and set the active HMC resource profile and status. 1671 * (direct 0x0500) and (direct 0x0501) 1672 */ 1673 struct i40e_aq_get_set_hmc_resource_profile { 1674 u8 pm_profile; 1675 u8 pe_vf_enabled; 1676 u8 reserved[14]; 1677 }; 1678 1679 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1680 1681 enum i40e_aq_hmc_profile { 1682 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1683 I40E_HMC_PROFILE_DEFAULT = 1, 1684 I40E_HMC_PROFILE_FAVOR_VF = 2, 1685 I40E_HMC_PROFILE_EQUAL = 3, 1686 }; 1687 1688 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1689 1690 /* set in param0 for get phy abilities to report qualified modules */ 1691 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1692 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1693 1694 enum i40e_aq_phy_type { 1695 I40E_PHY_TYPE_SGMII = 0x0, 1696 I40E_PHY_TYPE_1000BASE_KX = 0x1, 1697 I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1698 I40E_PHY_TYPE_10GBASE_KR = 0x3, 1699 I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1700 I40E_PHY_TYPE_XAUI = 0x5, 1701 I40E_PHY_TYPE_XFI = 0x6, 1702 I40E_PHY_TYPE_SFI = 0x7, 1703 I40E_PHY_TYPE_XLAUI = 0x8, 1704 I40E_PHY_TYPE_XLPPI = 0x9, 1705 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1706 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1707 I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1708 I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1709 I40E_PHY_TYPE_100BASE_TX = 0x11, 1710 I40E_PHY_TYPE_1000BASE_T = 0x12, 1711 I40E_PHY_TYPE_10GBASE_T = 0x13, 1712 I40E_PHY_TYPE_10GBASE_SR = 0x14, 1713 I40E_PHY_TYPE_10GBASE_LR = 0x15, 1714 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1715 I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1716 I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1717 I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1718 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1719 I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1720 I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1721 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1722 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1723 I40E_PHY_TYPE_25GBASE_KR = 0x1F, 1724 I40E_PHY_TYPE_25GBASE_CR = 0x20, 1725 I40E_PHY_TYPE_25GBASE_SR = 0x21, 1726 I40E_PHY_TYPE_25GBASE_LR = 0x22, 1727 I40E_PHY_TYPE_MAX 1728 }; 1729 1730 #define I40E_LINK_SPEED_100MB_SHIFT 0x1 1731 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2 1732 #define I40E_LINK_SPEED_10GB_SHIFT 0x3 1733 #define I40E_LINK_SPEED_40GB_SHIFT 0x4 1734 #define I40E_LINK_SPEED_20GB_SHIFT 0x5 1735 #define I40E_LINK_SPEED_25GB_SHIFT 0x6 1736 1737 enum i40e_aq_link_speed { 1738 I40E_LINK_SPEED_UNKNOWN = 0, 1739 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), 1740 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), 1741 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), 1742 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), 1743 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT), 1744 I40E_LINK_SPEED_25GB = (1 << I40E_LINK_SPEED_25GB_SHIFT), 1745 }; 1746 1747 struct i40e_aqc_module_desc { 1748 u8 oui[3]; 1749 u8 reserved1; 1750 u8 part_number[16]; 1751 u8 revision[4]; 1752 u8 reserved2[8]; 1753 }; 1754 1755 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); 1756 1757 struct i40e_aq_get_phy_abilities_resp { 1758 __le32 phy_type; /* bitmap using the above enum for offsets */ 1759 u8 link_speed; /* bitmap using the above enum bit patterns */ 1760 u8 abilities; 1761 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 1762 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 1763 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 1764 #define I40E_AQ_PHY_LINK_ENABLED 0x08 1765 #define I40E_AQ_PHY_AN_ENABLED 0x10 1766 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 1767 #define I40E_AQ_PHY_FEC_ABILITY_KR 0x40 1768 #define I40E_AQ_PHY_FEC_ABILITY_RS 0x80 1769 __le16 eee_capability; 1770 #define I40E_AQ_EEE_100BASE_TX 0x0002 1771 #define I40E_AQ_EEE_1000BASE_T 0x0004 1772 #define I40E_AQ_EEE_10GBASE_T 0x0008 1773 #define I40E_AQ_EEE_1000BASE_KX 0x0010 1774 #define I40E_AQ_EEE_10GBASE_KX4 0x0020 1775 #define I40E_AQ_EEE_10GBASE_KR 0x0040 1776 __le32 eeer_val; 1777 u8 d3_lpan; 1778 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 1779 u8 phy_type_ext; 1780 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0x01 1781 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0x02 1782 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 1783 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 1784 u8 mod_type_ext; 1785 u8 ext_comp_code; 1786 u8 phy_id[4]; 1787 u8 module_type[3]; 1788 u8 qualified_module_count; 1789 #define I40E_AQ_PHY_MAX_QMS 16 1790 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 1791 }; 1792 1793 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); 1794 1795 /* Set PHY Config (direct 0x0601) */ 1796 struct i40e_aq_set_phy_config { /* same bits as above in all */ 1797 __le32 phy_type; 1798 u8 link_speed; 1799 u8 abilities; 1800 /* bits 0-2 use the values from get_phy_abilities_resp */ 1801 #define I40E_AQ_PHY_ENABLE_LINK 0x08 1802 #define I40E_AQ_PHY_ENABLE_AN 0x10 1803 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 1804 __le16 eee_capability; 1805 __le32 eeer; 1806 u8 low_power_ctrl; 1807 u8 phy_type_ext; 1808 u8 fec_config; 1809 #define I40E_AQ_SET_FEC_ABILITY_KR (1 << 0) 1810 #define I40E_AQ_SET_FEC_ABILITY_RS (1 << 1) 1811 #define I40E_AQ_SET_FEC_REQUEST_KR (1 << 2) 1812 #define I40E_AQ_SET_FEC_REQUEST_RS (1 << 3) 1813 #define I40E_AQ_SET_FEC_AUTO (1 << 4) 1814 u8 reserved; 1815 }; 1816 1817 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 1818 1819 /* Set MAC Config command data structure (direct 0x0603) */ 1820 struct i40e_aq_set_mac_config { 1821 __le16 max_frame_size; 1822 u8 params; 1823 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 1824 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 1825 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 1826 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 1827 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 1828 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 1829 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 1830 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 1831 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 1832 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 1833 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 1834 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 1835 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 1836 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 1837 u8 tx_timer_priority; /* bitmap */ 1838 __le16 tx_timer_value; 1839 __le16 fc_refresh_threshold; 1840 u8 reserved[8]; 1841 }; 1842 1843 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 1844 1845 /* Restart Auto-Negotiation (direct 0x605) */ 1846 struct i40e_aqc_set_link_restart_an { 1847 u8 command; 1848 #define I40E_AQ_PHY_RESTART_AN 0x02 1849 #define I40E_AQ_PHY_LINK_ENABLE 0x04 1850 u8 reserved[15]; 1851 }; 1852 1853 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 1854 1855 /* Get Link Status cmd & response data structure (direct 0x0607) */ 1856 struct i40e_aqc_get_link_status { 1857 __le16 command_flags; /* only field set on command */ 1858 #define I40E_AQ_LSE_MASK 0x3 1859 #define I40E_AQ_LSE_NOP 0x0 1860 #define I40E_AQ_LSE_DISABLE 0x2 1861 #define I40E_AQ_LSE_ENABLE 0x3 1862 /* only response uses this flag */ 1863 #define I40E_AQ_LSE_IS_ENABLED 0x1 1864 u8 phy_type; /* i40e_aq_phy_type */ 1865 u8 link_speed; /* i40e_aq_link_speed */ 1866 u8 link_info; 1867 #define I40E_AQ_LINK_UP 0x01 /* obsolete */ 1868 #define I40E_AQ_LINK_UP_FUNCTION 0x01 1869 #define I40E_AQ_LINK_FAULT 0x02 1870 #define I40E_AQ_LINK_FAULT_TX 0x04 1871 #define I40E_AQ_LINK_FAULT_RX 0x08 1872 #define I40E_AQ_LINK_FAULT_REMOTE 0x10 1873 #define I40E_AQ_LINK_UP_PORT 0x20 1874 #define I40E_AQ_MEDIA_AVAILABLE 0x40 1875 #define I40E_AQ_SIGNAL_DETECT 0x80 1876 u8 an_info; 1877 #define I40E_AQ_AN_COMPLETED 0x01 1878 #define I40E_AQ_LP_AN_ABILITY 0x02 1879 #define I40E_AQ_PD_FAULT 0x04 1880 #define I40E_AQ_FEC_EN 0x08 1881 #define I40E_AQ_PHY_LOW_POWER 0x10 1882 #define I40E_AQ_LINK_PAUSE_TX 0x20 1883 #define I40E_AQ_LINK_PAUSE_RX 0x40 1884 #define I40E_AQ_QUALIFIED_MODULE 0x80 1885 u8 ext_info; 1886 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 1887 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 1888 #define I40E_AQ_LINK_TX_SHIFT 0x02 1889 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 1890 #define I40E_AQ_LINK_TX_ACTIVE 0x00 1891 #define I40E_AQ_LINK_TX_DRAINED 0x01 1892 #define I40E_AQ_LINK_TX_FLUSHED 0x03 1893 #define I40E_AQ_LINK_FORCED_40G 0x10 1894 /* 25G Error Codes */ 1895 #define I40E_AQ_25G_NO_ERR 0X00 1896 #define I40E_AQ_25G_NOT_PRESENT 0X01 1897 #define I40E_AQ_25G_NVM_CRC_ERR 0X02 1898 #define I40E_AQ_25G_SBUS_UCODE_ERR 0X03 1899 #define I40E_AQ_25G_SERDES_UCODE_ERR 0X04 1900 #define I40E_AQ_25G_NIMB_UCODE_ERR 0X05 1901 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 1902 __le16 max_frame_size; 1903 u8 config; 1904 #define I40E_AQ_CONFIG_FEC_KR_ENA 0x01 1905 #define I40E_AQ_CONFIG_FEC_RS_ENA 0x02 1906 #define I40E_AQ_CONFIG_CRC_ENA 0x04 1907 #define I40E_AQ_CONFIG_PACING_MASK 0x78 1908 u8 power_desc; 1909 #define I40E_AQ_LINK_POWER_CLASS_1 0x00 1910 #define I40E_AQ_LINK_POWER_CLASS_2 0x01 1911 #define I40E_AQ_LINK_POWER_CLASS_3 0x02 1912 #define I40E_AQ_LINK_POWER_CLASS_4 0x03 1913 #define I40E_AQ_PWR_CLASS_MASK 0x03 1914 u8 reserved[4]; 1915 }; 1916 1917 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 1918 1919 /* Set event mask command (direct 0x613) */ 1920 struct i40e_aqc_set_phy_int_mask { 1921 u8 reserved[8]; 1922 __le16 event_mask; 1923 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 1924 #define I40E_AQ_EVENT_MEDIA_NA 0x0004 1925 #define I40E_AQ_EVENT_LINK_FAULT 0x0008 1926 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 1927 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 1928 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 1929 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080 1930 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 1931 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 1932 u8 reserved1[6]; 1933 }; 1934 1935 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 1936 1937 /* Get Local AN advt register (direct 0x0614) 1938 * Set Local AN advt register (direct 0x0615) 1939 * Get Link Partner AN advt register (direct 0x0616) 1940 */ 1941 struct i40e_aqc_an_advt_reg { 1942 __le32 local_an_reg0; 1943 __le16 local_an_reg1; 1944 u8 reserved[10]; 1945 }; 1946 1947 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 1948 1949 /* Set Loopback mode (0x0618) */ 1950 struct i40e_aqc_set_lb_mode { 1951 __le16 lb_mode; 1952 #define I40E_AQ_LB_PHY_LOCAL 0x01 1953 #define I40E_AQ_LB_PHY_REMOTE 0x02 1954 #define I40E_AQ_LB_MAC_LOCAL 0x04 1955 u8 reserved[14]; 1956 }; 1957 1958 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 1959 1960 /* Set PHY Debug command (0x0622) */ 1961 struct i40e_aqc_set_phy_debug { 1962 u8 command_flags; 1963 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 1964 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 1965 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 1966 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 1967 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 1968 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 1969 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 1970 /* Disable link manageability on a single port */ 1971 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 1972 /* Disable link manageability on all ports needs both bits 4 and 5 */ 1973 #define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20 1974 u8 reserved[15]; 1975 }; 1976 1977 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 1978 1979 enum i40e_aq_phy_reg_type { 1980 I40E_AQC_PHY_REG_INTERNAL = 0x1, 1981 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 1982 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 1983 }; 1984 1985 /* Run PHY Activity (0x0626) */ 1986 struct i40e_aqc_run_phy_activity { 1987 __le16 activity_id; 1988 u8 flags; 1989 u8 reserved1; 1990 __le32 control; 1991 __le32 data; 1992 u8 reserved2[4]; 1993 }; 1994 1995 I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity); 1996 1997 1998 /* Set PHY Register command (0x0628) */ 1999 /* Get PHY Register command (0x0629) */ 2000 struct i40e_aqc_phy_register_access { 2001 u8 phy_interface; 2002 #define I40E_AQ_PHY_REG_ACCESS_INTERNAL 0 2003 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL 1 2004 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2 2005 u8 dev_addres; 2006 u8 reserved1[2]; 2007 u32 reg_address; 2008 u32 reg_value; 2009 u8 reserved2[4]; 2010 }; 2011 2012 I40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access); 2013 2014 2015 /* NVM Read command (indirect 0x0701) 2016 * NVM Erase commands (direct 0x0702) 2017 * NVM Update commands (indirect 0x0703) 2018 */ 2019 struct i40e_aqc_nvm_update { 2020 u8 command_flags; 2021 #define I40E_AQ_NVM_LAST_CMD 0x01 2022 #define I40E_AQ_NVM_FLASH_ONLY 0x80 2023 u8 module_pointer; 2024 __le16 length; 2025 __le32 offset; 2026 __le32 addr_high; 2027 __le32 addr_low; 2028 }; 2029 2030 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 2031 2032 /* NVM Config Read (indirect 0x0704) */ 2033 struct i40e_aqc_nvm_config_read { 2034 __le16 cmd_flags; 2035 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 2036 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 2037 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 2038 __le16 element_count; 2039 __le16 element_id; /* Feature/field ID */ 2040 __le16 element_id_msw; /* MSWord of field ID */ 2041 __le32 address_high; 2042 __le32 address_low; 2043 }; 2044 2045 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 2046 2047 /* NVM Config Write (indirect 0x0705) */ 2048 struct i40e_aqc_nvm_config_write { 2049 __le16 cmd_flags; 2050 __le16 element_count; 2051 u8 reserved[4]; 2052 __le32 address_high; 2053 __le32 address_low; 2054 }; 2055 2056 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 2057 2058 /* Used for 0x0704 as well as for 0x0705 commands */ 2059 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 2060 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \ 2061 (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) 2062 #define I40E_AQ_ANVM_FEATURE 0 2063 #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT) 2064 struct i40e_aqc_nvm_config_data_feature { 2065 __le16 feature_id; 2066 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 2067 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 2068 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 2069 __le16 feature_options; 2070 __le16 feature_selection; 2071 }; 2072 2073 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); 2074 2075 struct i40e_aqc_nvm_config_data_immediate_field { 2076 __le32 field_id; 2077 __le32 field_value; 2078 __le16 field_options; 2079 __le16 reserved; 2080 }; 2081 2082 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); 2083 2084 /* OEM Post Update (indirect 0x0720) 2085 * no command data struct used 2086 */ 2087 struct i40e_aqc_nvm_oem_post_update { 2088 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01 2089 u8 sel_data; 2090 u8 reserved[7]; 2091 }; 2092 2093 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update); 2094 2095 struct i40e_aqc_nvm_oem_post_update_buffer { 2096 u8 str_len; 2097 u8 dev_addr; 2098 __le16 eeprom_addr; 2099 u8 data[36]; 2100 }; 2101 2102 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer); 2103 2104 /* Thermal Sensor (indirect 0x0721) 2105 * read or set thermal sensor configs and values 2106 * takes a sensor and command specific data buffer, not detailed here 2107 */ 2108 struct i40e_aqc_thermal_sensor { 2109 u8 sensor_action; 2110 #define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0 2111 #define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1 2112 #define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2 2113 u8 reserved[7]; 2114 __le32 addr_high; 2115 __le32 addr_low; 2116 }; 2117 2118 I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor); 2119 2120 /* Send to PF command (indirect 0x0801) id is only used by PF 2121 * Send to VF command (indirect 0x0802) id is only used by PF 2122 * Send to Peer PF command (indirect 0x0803) 2123 */ 2124 struct i40e_aqc_pf_vf_message { 2125 __le32 id; 2126 u8 reserved[4]; 2127 __le32 addr_high; 2128 __le32 addr_low; 2129 }; 2130 2131 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 2132 2133 /* Alternate structure */ 2134 2135 /* Direct write (direct 0x0900) 2136 * Direct read (direct 0x0902) 2137 */ 2138 struct i40e_aqc_alternate_write { 2139 __le32 address0; 2140 __le32 data0; 2141 __le32 address1; 2142 __le32 data1; 2143 }; 2144 2145 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 2146 2147 /* Indirect write (indirect 0x0901) 2148 * Indirect read (indirect 0x0903) 2149 */ 2150 2151 struct i40e_aqc_alternate_ind_write { 2152 __le32 address; 2153 __le32 length; 2154 __le32 addr_high; 2155 __le32 addr_low; 2156 }; 2157 2158 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 2159 2160 /* Done alternate write (direct 0x0904) 2161 * uses i40e_aq_desc 2162 */ 2163 struct i40e_aqc_alternate_write_done { 2164 __le16 cmd_flags; 2165 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 2166 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 2167 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 2168 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2 2169 u8 reserved[14]; 2170 }; 2171 2172 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 2173 2174 /* Set OEM mode (direct 0x0905) */ 2175 struct i40e_aqc_alternate_set_mode { 2176 __le32 mode; 2177 #define I40E_AQ_ALTERNATE_MODE_NONE 0 2178 #define I40E_AQ_ALTERNATE_MODE_OEM 1 2179 u8 reserved[12]; 2180 }; 2181 2182 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 2183 2184 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 2185 2186 /* async events 0x10xx */ 2187 2188 /* Lan Queue Overflow Event (direct, 0x1001) */ 2189 struct i40e_aqc_lan_overflow { 2190 __le32 prtdcb_rupto; 2191 __le32 otx_ctl; 2192 u8 reserved[8]; 2193 }; 2194 2195 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 2196 2197 /* Get LLDP MIB (indirect 0x0A00) */ 2198 struct i40e_aqc_lldp_get_mib { 2199 u8 type; 2200 u8 reserved1; 2201 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 2202 #define I40E_AQ_LLDP_MIB_LOCAL 0x0 2203 #define I40E_AQ_LLDP_MIB_REMOTE 0x1 2204 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 2205 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 2206 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 2207 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 2208 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 2209 #define I40E_AQ_LLDP_TX_SHIFT 0x4 2210 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 2211 /* TX pause flags use I40E_AQ_LINK_TX_* above */ 2212 __le16 local_len; 2213 __le16 remote_len; 2214 u8 reserved2[2]; 2215 __le32 addr_high; 2216 __le32 addr_low; 2217 }; 2218 2219 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 2220 2221 /* Configure LLDP MIB Change Event (direct 0x0A01) 2222 * also used for the event (with type in the command field) 2223 */ 2224 struct i40e_aqc_lldp_update_mib { 2225 u8 command; 2226 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 2227 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 2228 u8 reserved[7]; 2229 __le32 addr_high; 2230 __le32 addr_low; 2231 }; 2232 2233 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 2234 2235 /* Add LLDP TLV (indirect 0x0A02) 2236 * Delete LLDP TLV (indirect 0x0A04) 2237 */ 2238 struct i40e_aqc_lldp_add_tlv { 2239 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2240 u8 reserved1[1]; 2241 __le16 len; 2242 u8 reserved2[4]; 2243 __le32 addr_high; 2244 __le32 addr_low; 2245 }; 2246 2247 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 2248 2249 /* Update LLDP TLV (indirect 0x0A03) */ 2250 struct i40e_aqc_lldp_update_tlv { 2251 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2252 u8 reserved; 2253 __le16 old_len; 2254 __le16 new_offset; 2255 __le16 new_len; 2256 __le32 addr_high; 2257 __le32 addr_low; 2258 }; 2259 2260 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 2261 2262 /* Stop LLDP (direct 0x0A05) */ 2263 struct i40e_aqc_lldp_stop { 2264 u8 command; 2265 #define I40E_AQ_LLDP_AGENT_STOP 0x0 2266 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 2267 u8 reserved[15]; 2268 }; 2269 2270 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 2271 2272 /* Start LLDP (direct 0x0A06) */ 2273 2274 struct i40e_aqc_lldp_start { 2275 u8 command; 2276 #define I40E_AQ_LLDP_AGENT_START 0x1 2277 u8 reserved[15]; 2278 }; 2279 2280 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 2281 2282 /* Get CEE DCBX Oper Config (0x0A07) 2283 * uses the generic descriptor struct 2284 * returns below as indirect response 2285 */ 2286 2287 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2288 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2289 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2290 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2291 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2292 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2293 2294 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2295 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2296 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2297 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2298 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2299 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2300 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8 2301 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT) 2302 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB 2303 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT) 2304 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10 2305 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT) 2306 2307 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with 2308 * word boundary layout issues, which the Linux compilers silently deal 2309 * with by adding padding, making the actual struct larger than designed. 2310 * However, the FW compiler for the NIC is less lenient and complains 2311 * about the struct. Hence, the struct defined here has an extra byte in 2312 * fields reserved3 and reserved4 to directly acknowledge that padding, 2313 * and the new length is used in the length check macro. 2314 */ 2315 struct i40e_aqc_get_cee_dcb_cfg_v1_resp { 2316 u8 reserved1; 2317 u8 oper_num_tc; 2318 u8 oper_prio_tc[4]; 2319 u8 reserved2; 2320 u8 oper_tc_bw[8]; 2321 u8 oper_pfc_en; 2322 u8 reserved3[2]; 2323 __le16 oper_app_prio; 2324 u8 reserved4[2]; 2325 __le16 tlv_status; 2326 }; 2327 2328 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp); 2329 2330 struct i40e_aqc_get_cee_dcb_cfg_resp { 2331 u8 oper_num_tc; 2332 u8 oper_prio_tc[4]; 2333 u8 oper_tc_bw[8]; 2334 u8 oper_pfc_en; 2335 __le16 oper_app_prio; 2336 __le32 tlv_status; 2337 u8 reserved[12]; 2338 }; 2339 2340 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp); 2341 2342 /* Set Local LLDP MIB (indirect 0x0A08) 2343 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx 2344 */ 2345 struct i40e_aqc_lldp_set_local_mib { 2346 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0 2347 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \ 2348 SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) 2349 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0 2350 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1) 2351 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \ 2352 SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT) 2353 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1 2354 u8 type; 2355 u8 reserved0; 2356 __le16 length; 2357 u8 reserved1[4]; 2358 __le32 address_high; 2359 __le32 address_low; 2360 }; 2361 2362 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib); 2363 2364 struct i40e_aqc_lldp_set_local_mib_resp { 2365 #define SET_LOCAL_MIB_RESP_EVENT_TRIGGERED_MASK 0x01 2366 u8 status; 2367 u8 reserved[15]; 2368 }; 2369 2370 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_lldp_set_local_mib_resp); 2371 2372 /* Stop/Start LLDP Agent (direct 0x0A09) 2373 * Used for stopping/starting specific LLDP agent. e.g. DCBx 2374 */ 2375 struct i40e_aqc_lldp_stop_start_specific_agent { 2376 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0 2377 #define I40E_AQC_START_SPECIFIC_AGENT_MASK \ 2378 (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT) 2379 u8 command; 2380 u8 reserved[15]; 2381 }; 2382 2383 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent); 2384 2385 /* Add Udp Tunnel command and completion (direct 0x0B00) */ 2386 struct i40e_aqc_add_udp_tunnel { 2387 __le16 udp_port; 2388 u8 reserved0[3]; 2389 u8 protocol_type; 2390 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2391 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2392 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2393 #define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11 2394 u8 reserved1[10]; 2395 }; 2396 2397 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2398 2399 struct i40e_aqc_add_udp_tunnel_completion { 2400 __le16 udp_port; 2401 u8 filter_entry_index; 2402 u8 multiple_pfs; 2403 #define I40E_AQC_SINGLE_PF 0x0 2404 #define I40E_AQC_MULTIPLE_PFS 0x1 2405 u8 total_filters; 2406 u8 reserved[11]; 2407 }; 2408 2409 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2410 2411 /* remove UDP Tunnel command (0x0B01) */ 2412 struct i40e_aqc_remove_udp_tunnel { 2413 u8 reserved[2]; 2414 u8 index; /* 0 to 15 */ 2415 u8 reserved2[13]; 2416 }; 2417 2418 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2419 2420 struct i40e_aqc_del_udp_tunnel_completion { 2421 __le16 udp_port; 2422 u8 index; /* 0 to 15 */ 2423 u8 multiple_pfs; 2424 u8 total_filters_used; 2425 u8 reserved1[11]; 2426 }; 2427 2428 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2429 2430 struct i40e_aqc_get_set_rss_key { 2431 #define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15) 2432 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0 2433 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \ 2434 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) 2435 __le16 vsi_id; 2436 u8 reserved[6]; 2437 __le32 addr_high; 2438 __le32 addr_low; 2439 }; 2440 2441 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key); 2442 2443 struct i40e_aqc_get_set_rss_key_data { 2444 u8 standard_rss_key[0x28]; 2445 u8 extended_hash_key[0xc]; 2446 }; 2447 2448 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data); 2449 2450 struct i40e_aqc_get_set_rss_lut { 2451 #define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15) 2452 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0 2453 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \ 2454 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) 2455 __le16 vsi_id; 2456 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0 2457 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \ 2458 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) 2459 2460 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0 2461 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1 2462 __le16 flags; 2463 u8 reserved[4]; 2464 __le32 addr_high; 2465 __le32 addr_low; 2466 }; 2467 2468 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut); 2469 2470 /* tunnel key structure 0x0B10 */ 2471 2472 struct i40e_aqc_tunnel_key_structure { 2473 u8 key1_off; 2474 u8 key2_off; 2475 u8 key1_len; /* 0 to 15 */ 2476 u8 key2_len; /* 0 to 15 */ 2477 u8 flags; 2478 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2479 /* response flags */ 2480 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2481 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2482 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2483 u8 network_key_index; 2484 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2485 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2486 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2487 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2488 u8 reserved[10]; 2489 }; 2490 2491 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2492 2493 /* OEM mode commands (direct 0xFE0x) */ 2494 struct i40e_aqc_oem_param_change { 2495 __le32 param_type; 2496 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2497 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2498 #define I40E_AQ_OEM_PARAM_MAC 2 2499 __le32 param_value1; 2500 __le16 param_value2; 2501 u8 reserved[6]; 2502 }; 2503 2504 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2505 2506 struct i40e_aqc_oem_state_change { 2507 __le32 state; 2508 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2509 #define I40E_AQ_OEM_STATE_LINK_UP 0x1 2510 u8 reserved[12]; 2511 }; 2512 2513 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2514 2515 /* Initialize OCSD (0xFE02, direct) */ 2516 struct i40e_aqc_opc_oem_ocsd_initialize { 2517 u8 type_status; 2518 u8 reserved1[3]; 2519 __le32 ocsd_memory_block_addr_high; 2520 __le32 ocsd_memory_block_addr_low; 2521 __le32 requested_update_interval; 2522 }; 2523 2524 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); 2525 2526 /* Initialize OCBB (0xFE03, direct) */ 2527 struct i40e_aqc_opc_oem_ocbb_initialize { 2528 u8 type_status; 2529 u8 reserved1[3]; 2530 __le32 ocbb_memory_block_addr_high; 2531 __le32 ocbb_memory_block_addr_low; 2532 u8 reserved2[4]; 2533 }; 2534 2535 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); 2536 2537 /* debug commands */ 2538 2539 /* get device id (0xFF00) uses the generic structure */ 2540 2541 /* set test more (0xFF01, internal) */ 2542 2543 struct i40e_acq_set_test_mode { 2544 u8 mode; 2545 #define I40E_AQ_TEST_PARTIAL 0 2546 #define I40E_AQ_TEST_FULL 1 2547 #define I40E_AQ_TEST_NVM 2 2548 u8 reserved[3]; 2549 u8 command; 2550 #define I40E_AQ_TEST_OPEN 0 2551 #define I40E_AQ_TEST_CLOSE 1 2552 #define I40E_AQ_TEST_INC 2 2553 u8 reserved2[3]; 2554 __le32 address_high; 2555 __le32 address_low; 2556 }; 2557 2558 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2559 2560 /* Debug Read Register command (0xFF03) 2561 * Debug Write Register command (0xFF04) 2562 */ 2563 struct i40e_aqc_debug_reg_read_write { 2564 __le32 reserved; 2565 __le32 address; 2566 __le32 value_high; 2567 __le32 value_low; 2568 }; 2569 2570 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2571 2572 /* Scatter/gather Reg Read (indirect 0xFF05) 2573 * Scatter/gather Reg Write (indirect 0xFF06) 2574 */ 2575 2576 /* i40e_aq_desc is used for the command */ 2577 struct i40e_aqc_debug_reg_sg_element_data { 2578 __le32 address; 2579 __le32 value; 2580 }; 2581 2582 /* Debug Modify register (direct 0xFF07) */ 2583 struct i40e_aqc_debug_modify_reg { 2584 __le32 address; 2585 __le32 value; 2586 __le32 clear_mask; 2587 __le32 set_mask; 2588 }; 2589 2590 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 2591 2592 /* dump internal data (0xFF08, indirect) */ 2593 2594 #define I40E_AQ_CLUSTER_ID_AUX 0 2595 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 2596 #define I40E_AQ_CLUSTER_ID_TXSCHED 2 2597 #define I40E_AQ_CLUSTER_ID_HMC 3 2598 #define I40E_AQ_CLUSTER_ID_MAC0 4 2599 #define I40E_AQ_CLUSTER_ID_MAC1 5 2600 #define I40E_AQ_CLUSTER_ID_MAC2 6 2601 #define I40E_AQ_CLUSTER_ID_MAC3 7 2602 #define I40E_AQ_CLUSTER_ID_DCB 8 2603 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9 2604 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10 2605 #define I40E_AQ_CLUSTER_ID_ALTRAM 11 2606 2607 struct i40e_aqc_debug_dump_internals { 2608 u8 cluster_id; 2609 u8 table_id; 2610 __le16 data_size; 2611 __le32 idx; 2612 __le32 address_high; 2613 __le32 address_low; 2614 }; 2615 2616 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 2617 2618 struct i40e_aqc_debug_modify_internals { 2619 u8 cluster_id; 2620 u8 cluster_specific_params[7]; 2621 __le32 address_high; 2622 __le32 address_low; 2623 }; 2624 2625 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 2626 2627 #endif /* _I40E_ADMINQ_CMD_H_ */ 2628