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Searched refs:fault (Results 1 – 25 of 201) sorted by relevance

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/titanic_44/usr/src/cmd/fm/dicts/
H A DSUN4U.dict30 fault.memory.page=1
31 fault.memory.dimm=2
32 fault.memory.bank=3
33 fault.cpu.ultraSPARC-III.dcache=4
34 fault.cpu.ultraSPARC-III.icache=5
35 fault.cpu.ultraSPARC-III.l2cachedata=6
36 fault.cpu.ultraSPARC-III.l2cachetag=7
37 fault.cpu.ultraSPARC-IIIi.dcache=8
38 fault.cpu.ultraSPARC-IIIi.icache=9
39 fault.cpu.ultraSPARC-IIIi.l2cachedata=10
[all …]
H A DSUN4V.dict29 fault.cpu.ultraSPARC-T1.ireg=1
30 fault.cpu.ultraSPARC-T1.freg=2
31 fault.cpu.ultraSPARC-T1.itlb=3
32 fault.cpu.ultraSPARC-T1.dtlb=4
33 fault.cpu.ultraSPARC-T1.icache=5
34 fault.cpu.ultraSPARC-T1.dcache=6
35 fault.cpu.ultraSPARC-T1.mau=7
36 fault.cpu.ultraSPARC-T1.l2cachedata=8
37 fault.cpu.ultraSPARC-T1.l2cachetag=9
38 fault.cpu.ultraSPARC-T1.l2cachectl=10
[all …]
H A DINTEL.dict29 fault.cpu.intel.internal=1
30 fault.cpu.intel.l0cache=2
31 fault.cpu.intel.l1cache=3
32 fault.cpu.intel.l2cache=4
33 fault.cpu.intel.cache=5
34 fault.cpu.intel.l0dtlb=6
35 fault.cpu.intel.l1dtlb=7
36 fault.cpu.intel.l2dtlb=8
37 fault.cpu.intel.dtlb=9
38 fault.cpu.intel.l0itlb=10
[all …]
H A DSCF.dict31 fault.chassis.SPARC-Enterprise.if.fe-asic-clk=1
32 fault.chassis.SPARC-Enterprise.if.fe-clk-cable=2
33 fault.chassis.SPARC-Enterprise.asic.clk.fe=3
34 fault.chassis.SPARC-Enterprise.asic.clk.test=4
35 fault.chassis.SPARC-Enterprise.cpu.SPARC64-VI.fe=11
36 fault.chassis.SPARC-Enterprise.cpu.SPARC64-VI.core.fe=12
37 fault.chassis.SPARC-Enterprise.cpu.SPARC64-VI.core.strand.fe=13
38 fault.chassis.SPARC-Enterprise.cpu.SPARC64-VI.se=14
39 fault.chassis.SPARC-Enterprise.cpu.SPARC64-VI.core.se=15
40 fault.chassis.SPARC-Enterprise.cpu.SPARC64-VI.core.se-offlinereq=16
[all …]
H A DPCIEX.dict29 fault.io.pciex.device-interr=0
30 fault.io.pciex.device-interr fault.io.pciex.device-invreq=1
31 fault.io.pciex.bus-noresp fault.io.pciex.device-noresp=2
32 fault.io.pciex.bus-linkerr fault.io.pciex.device-interr=3
33 fault.io.pci.bus-linkerr fault.io.pciex.device-interr=4
34 fault.io.pci.device-invreq=5
35 fault.io.pci.device-invreq fault.io.pciex.device-interr=6
36 fault.io.pci.device-interr fault.io.pciex.device-invreq=7
37 fault.io.pciex.device-invreq=8
38 fault.io.pci.device-noresp fault.io.pciex.device-invreq=9
[all …]
H A DGMCA.dict29 fault.cpu.generic-x86.internal=1
30 fault.cpu.generic-x86.l0cache=2
31 fault.cpu.generic-x86.l1cache=3
32 fault.cpu.generic-x86.l2cache=4
33 fault.cpu.generic-x86.cache=5
34 fault.cpu.generic-x86.l0dtlb=6
35 fault.cpu.generic-x86.l1dtlb=7
36 fault.cpu.generic-x86.l2dtlb=8
37 fault.cpu.generic-x86.dtlb=9
38 fault.cpu.generic-x86.l0itlb=10
[all …]
H A DSUN4.dict31 fault.io.fire.asic=0
32 fault.io.ebus=1
33 fault.io.datapath=2
34 fault.io.hbus=3
35 fault.io.fire.pciex.device=4
37 fault.io.datapath fault.io.fire.asic=6
38 fault.io.fire.asic fault.io.fire.pciex.device=7
40 fault.io.fire.pci.device fault.io.fire.pciex.device=9
41 fault.io.fire.pci.device=10
42 defect.io.fire.pciex.driver fault.io.datapath fault.io.fire.asic=11
[all …]
H A DAMD.dict31 fault.memory.page=1
32 fault.memory.dimm_sb=2
33 fault.memory.dimm_ck=3
34 fault.memory.dimm_ue=4
35 fault.cpu.amd.l2cachedata=5
36 fault.cpu.amd.l2cachetag=6
37 fault.cpu.amd.icachedata=7
38 fault.cpu.amd.icachetag=8
39 fault.cpu.amd.icachestag=9
40 fault.cpu.amd.dcachedata=10
[all …]
H A DPCI.dict30 fault.io.pci.bus=1
31 defect.io.pci.driver fault.io.pci.bus=2
32 fault.io.pci.device=3
33 defect.io.pci.driver fault.io.pci.device=4
34 fault.io.pci.bus fault.io.pci.device=5
35 defect.io.pci.driver fault.io.pci.bus fault.io.pci.device=6
36 fault.io.pci.device-interr=7
37 fault.io.pci.bus-linkerr fault.io.pci.device-interr=8
38 fault.io.pci.device-invreq fault.io.pci.device-noresp=9
39 fault.io.pci.device-interr fault.io.pci.device-invreq=10
[all …]
H A DSTORAGE.dict29 fault.config.fan-fail=1
30 fault.config.fantray-fail=2
31 fault.config.psu-fail=3
32 fault.device.controller.fail=4
33 fault.device.ethernet.fail=5
34 fault.device.fan.fail=6
35 fault.device.psu.fail=7
36 fault.device.sas-expander.fail=8
37 fault.device.unusable-chassis-id=9
38 fault.io.i2c.fail=10
[all …]
H A DSUN4U.po29 # keys: fault.memory.page
45 # keys: fault.memory.dimm
61 # keys: fault.memory.bank
77 # keys: fault.cpu.ultraSPARC-III.dcache
86 msgstr "The fault manager will attempt to remove the affected CPU from service."
93 # keys: fault.cpu.ultraSPARC-III.icache
102 msgstr "The fault manager will attempt to remove the affected CPU from service."
109 # keys: fault.cpu.ultraSPARC-III.l2cachedata
118 msgstr "The fault manager will attempt to remove the affected CPU from service."
125 # keys: fault.cpu.ultraSPARC-III.l2cachetag
[all …]
/titanic_44/usr/src/lib/fm/libdiagcode/common/tests/
H A DSAMPLE2.dict34 fault.one=182736
35 fault.two=7958473
36 fault.one fault.two=1501916219321029
37 fault.three=0x1183B380
38 fault.three fault.two=36029071898968063
39 fault.one fault.three fault.two=36029071898968064
40 fault.one fault.three=2
45 #TEST:key2code:0:fault.two fault.one:SAMPLE2-D2NC-G0XL-HNDC-L0
46 #TEST:key2code:0:fault.three fault.two:SAMPLE2-EYYY-YYYY-YYYY-E8
47 #TEST:key2code:0:fault.one fault.three fault.two:SAMPLE2-F000-0000-0000-000E-XN
[all …]
H A DSAMPLE3.dict34 fault.one=36029071898968063
35 fault.two=36029071898968064
36 fault.three=36029071898968065
38 fault.a00=1
39 fault.a01=2
40 fault.a02=6029071898968
41 fault.a03=11111
42 fault.a04=2222222
43 fault.a05=333333333
44 fault.a06=1234567890
[all …]
H A DSAMPLE0.dict35 # here's a worked by hand example for key: "fault.one fault.two"
58 fault.one fault.three fault.two=2 "this is all three faults"
59 fault.one fault.three=1
60 fault.one=7
61 fault.two=6
62 fault.one fault.two=5
63 fault.three=4
64 fault.three fault.two=3
72 #TEST:key2code:0:fault.two fault.one:SAMPLE0-8000-5V
73 #TEST:key2code:0:fault.one fault.two:SAMPLE0-8000-5V
[all …]
H A DSAMPLE1.dict35 fault.z.one=2097150
36 fault.y.two=2097151
37 fault.y.two fault.z.one=2097152
38 fault.x.three=0x200001
39 fault.x.three fault.y.two=274880004090
40 fault.x.three fault.y.two fault.z.one=1928
41 fault.x.three fault.z.one=2
46 #TEST:key2code:0:fault.z.one:SAMPLE1-9YYY-X6
47 #TEST:key2code:0:fault.y.two:SAMPLE1-9YYY-YT
48 #TEST:key2code:0:fault.x.three:SAMPLE1-A000-0000-FJ
[all …]
H A DBADBITS.dict35 fault.one=777
36 fault.two=6
37 fault.one fault.two=5
38 fault.three=4
39 fault.three fault.two=3
40 fault.one fault.three=1
43 #TEST:key2code:0:fault.one:BADBITS-800R-99
44 #TEST:key2code:0:fault.one fault.one:BADBITS-800R-99
45 #TEST:key2code:0:fault.one fault.two fault.one:BADBITS-8000-5T
H A DMALFORMED.dict33 fault.one fault.three fault.two 2
34 fault.one fault.three=1
36 fault.two=6
37 fault.one fault.two=5
38 fault.three=4
39 fault.three fault.two=3
42 #TEST:key2code:0:fault.two fault.three:MALFORMED-8000-3N
H A DBADMAXKEY.dict35 fault.two=6
36 fault.one fault.two=5
37 fault.three=4
38 fault.one fault.three fault.two=3
39 fault.one fault.three=1
42 #TEST:key2code:0:fault.one fault.three fault.two:BADMAXKEY-8000-30
/titanic_44/usr/src/cmd/fm/eversholt/files/common/
H A Dstorage.esc32 event fault.config.fan-fail@ses-enclosure;
33 event fault.config.fantray-fail@ses-enclosure;
34 event fault.config.psu-fail@ses-enclosure;
35 event fault.device.controller.fail@controller;
36 event fault.device.ethernet.fail@controller;
37 event fault.device.ethernet.fail@sas-expander;
38 event fault.device.fan.fail@fan;
39 event fault.device.fan.fail@fanmodule;
40 event fault.device.psu.fail@psu;
41 event fault.device.psu.fail@psu;
[all …]
H A Dsensor.esc36 * Generic fan/psu fault events.
38 event fault.fan.failed@fan;
39 event fault.psu.failed@psu;
43 * Fine-grained fan/psu fault events
45 event fault.fan.failed-pred@fan;
46 event fault.psu.failed-int@psu;
47 event fault.psu.failed-ext@psu;
48 event fault.psu.failed-pred@psu;
59 prop fault.fan.failed@fan ->
63 prop fault.fan.failed-pred@fan ->
[all …]
/titanic_44/usr/src/cmd/fm/modules/SUNW,Netra-T5440/etm/
H A Detm.conf27 subscribe fault.cpu.*
28 subscribe fault.memory.*
29 subscribe fault.io.fire.*
30 subscribe fault.io.pci.*
31 subscribe fault.io.pciex.*
32 subscribe fault.io.n2.*
33 subscribe fault.io.vf.*
34 subscribe fault.asic.ultraSPARC-T2plus.*
/titanic_44/usr/src/cmd/fm/modules/SUNW,T5140/etm/
H A Detm.conf27 subscribe fault.cpu.*
28 subscribe fault.memory.*
29 subscribe fault.io.fire.*
30 subscribe fault.io.pci.*
31 subscribe fault.io.pciex.*
32 subscribe fault.io.n2.*
33 subscribe fault.io.vf.*
34 subscribe fault.asic.ultraSPARC-T2plus.*
/titanic_44/usr/src/cmd/fm/modules/SUNW,USBRDT-5240/etm/
H A Detm.conf27 subscribe fault.cpu.*
28 subscribe fault.memory.*
29 subscribe fault.io.fire.*
30 subscribe fault.io.pci.*
31 subscribe fault.io.pciex.*
32 subscribe fault.io.n2.*
33 subscribe fault.io.vf.*
/titanic_44/usr/src/cmd/fm/eversholt/files/sparc/sun4v/
H A Dgmem.esc53 * fault.memory.generic-sparc.bank & fault.memory.generic-sparc.page
64 event fault.memory.bank@DIMMPATH; \
66 prop fault.memory.bank@DIMMPATH \
81 event fault.memory.page@DIMMPATH, \
84 prop fault.memory.page@DIMMPATH \
112 event fault.memory.memlink@CHIP,
114 event fault.memory.memlink@MEM_BUFF,
116 event fault.memory.memlink@MEM_CTRL,
120 * 1. if ereport has both sender & detector: membuf-crc errors will fault
142 prop fault.memory.memlink@CHIP
[all …]
/titanic_44/usr/src/cmd/fm/eversholt/files/i386/i86pc/
H A Dintel.esc50 * If the error is uncorrected we produce a fault immediately, otherwise
51 * we diagnose it to an upset and decalre a fault when the SERD engine
57 event fault.cpu.intel.internal@chip/core/strand,
60 prop fault.cpu.intel.internal@chip/core/strand
127 * We resist the temptation propogate, for example, a single dcache fault
129 * Instead we will diagnose a distinct fault for each possible cache level,
132 * Corrected errors are SERDed and produce a fault when the engine fires;
133 * the same fault is diagnosed immediately for a corresponding uncorrected
139 event fault.cpu.intel.fltleaf@chip/core/strand, \
142 prop fault.cpu.intel.fltleaf@chip/core/strand (0)-> \
[all …]

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