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Searched refs:emac_base (Results 1 – 5 of 5) sorted by relevance

/titanic_44/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/
H A Dlm_hw_access.c927 u32_t emac_base = (port_idx) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; in lm_override_led_value() local
936 reg_val = REG_RD(pdev, emac_base + EMAC_REG_EMAC_LED); in lm_override_led_value()
941 REG_WR(pdev, emac_base+ EMAC_REG_EMAC_LED, reg_val); in lm_override_led_value()
945 reg_val = REG_RD(pdev, emac_base + EMAC_REG_EMAC_LED); in lm_override_led_value()
950 REG_WR(pdev, emac_base+ EMAC_REG_EMAC_LED, reg_val); in lm_override_led_value()
954 reg_val = REG_RD(pdev, emac_base + EMAC_REG_EMAC_LED); in lm_override_led_value()
959 REG_WR(pdev, emac_base+ EMAC_REG_EMAC_LED, reg_val); in lm_override_led_value()
963 reg_val = REG_RD(pdev, emac_base + EMAC_REG_EMAC_LED); in lm_override_led_value()
968 REG_WR(pdev, emac_base+ EMAC_REG_EMAC_LED, reg_val); in lm_override_led_value()
989 reg_val = REG_RD(pdev, emac_base + EMAC_REG_EMAC_LED); in lm_override_led_value()
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H A Dlm_phy.c247 u32_t emac_base = (port?GRCBASE_EMAC1:GRCBASE_EMAC0); in lm_mwrite() local
255 tmp=REG_RD(pdev,emac_base+EMAC_REG_EMAC_MDIO_MODE); in lm_mwrite()
258 REG_WR(pdev,emac_base+EMAC_REG_EMAC_MDIO_MODE,tmp); in lm_mwrite()
267 REG_WR(pdev,emac_base+EMAC_REG_EMAC_MDIO_COMM,tmp); in lm_mwrite()
274 tmp=REG_RD(pdev,emac_base+EMAC_REG_EMAC_MDIO_COMM); in lm_mwrite()
295 tmp=REG_RD(pdev,emac_base+EMAC_REG_EMAC_MDIO_MODE); in lm_mwrite()
298 REG_WR(pdev,emac_base+EMAC_REG_EMAC_MDIO_MODE,tmp); in lm_mwrite()
321 u32_t emac_base = (port?GRCBASE_EMAC1:GRCBASE_EMAC0); in lm_mread() local
329 val=REG_RD(pdev,emac_base+EMAC_REG_EMAC_MDIO_MODE); in lm_mread()
332 REG_WR(pdev,emac_base+EMAC_REG_EMAC_MDIO_MODE,val); in lm_mread()
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H A Dlm_power.c295 u32_t emac_base = 0 ; in lm_set_d3_mpkt() local
315 emac_base = ( 0 == PORT_ID(pdev) ) ? GRCBASE_EMAC0 : GRCBASE_EMAC1 ; in lm_set_d3_mpkt()
321 REG_WR(pdev, emac_base+ offset , b_enable_mpkt ? val:0); in lm_set_d3_mpkt()
326 REG_WR(pdev, emac_base+ offset, b_enable_mpkt ? val:0); in lm_set_d3_mpkt()
H A Dlm_stats.c694 u32_t emac_base = 0 ; in lm_stats_clear_emac_stats() local
704 emac_base = ( 0 == PORT_ID(pdev) ) ? GRCBASE_EMAC0 : GRCBASE_EMAC1 ; in lm_stats_clear_emac_stats()
710 …dummy = REG_RD( pdev, emac_base + reg_start[i]+(j*sizeof(u32_t))) ; /*Clear stats registers by rea… in lm_stats_clear_emac_stats()
1199 const u32_t emac_base = (PORT_ID(pdev)==0) ? GRCBASE_EMAC0 : GRCBASE_EMAC1; in lm_stats_hw_setup_emac() local
1207 sges[0].source_offset = emac_base + EMAC_REG_EMAC_RX_STAT_IFHCINOCTETS; in lm_stats_hw_setup_emac()
1211 sges[1].source_offset = emac_base + EMAC_REG_EMAC_RX_STAT_FALSECARRIERERRORS; in lm_stats_hw_setup_emac()
1215 sges[2].source_offset = emac_base + EMAC_REG_EMAC_TX_STAT_IFHCOUTOCTETS; in lm_stats_hw_setup_emac()
/titanic_44/usr/src/uts/common/io/bnxe/577xx/common/
H A Dbnxe_clc.c69 #define EMAC_RD(cb, reg) REG_RD(cb, emac_base + reg)
70 #define EMAC_WR(cb, reg, val) REG_WR(cb, emac_base + reg, val)
1557 u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; in elink_emac_get_pfc_stat() local
1564 val_xoff = REG_RD(cb, emac_base + in elink_emac_get_pfc_stat()
1567 val_xon = REG_RD(cb, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD); in elink_emac_get_pfc_stat()
1573 val_xoff = REG_RD(cb, emac_base + in elink_emac_get_pfc_stat()
1576 val_xon = REG_RD(cb, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT); in elink_emac_get_pfc_stat()
1607 u32 emac_base) in elink_set_mdio_clk() argument
1614 cur_mode = REG_RD(cb, emac_base + EMAC_REG_EMAC_MDIO_MODE); in elink_set_mdio_clk()
1632 REG_WR(cb, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode); in elink_set_mdio_clk()
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