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Searched refs:devhandle_t (Results 1 – 16 of 16) sorted by relevance

/titanic_44/usr/src/uts/sun4v/io/px/
H A Dpx_lib4v.h129 extern uint64_t hvio_iommu_map(devhandle_t dev_hdl, tsbid_t tsbid,
132 extern uint64_t hvio_iommu_demap(devhandle_t dev_hdl, tsbid_t tsbid,
134 extern uint64_t hvio_iommu_getmap(devhandle_t dev_hdl, tsbid_t tsbid,
136 extern uint64_t hvio_iommu_getbypass(devhandle_t dev_hdl, r_addr_t ra,
138 extern uint64_t hvio_dma_sync(devhandle_t dev_hdl, r_addr_t ra,
145 extern uint64_t hvio_msiq_conf(devhandle_t dev_hdl, msiqid_t msiq_id,
147 extern uint64_t hvio_msiq_info(devhandle_t dev_hdl, msiqid_t msiq_id,
149 extern uint64_t hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id,
151 extern uint64_t hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id,
153 extern uint64_t hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id,
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H A Dpx_hcall.s41 hvio_iommu_map(devhandle_t dev_hdl, tsbid_t tsbid, pages_t pages,
48 hvio_iommu_demap(devhandle_t dev_hdl, tsbid_t tsbid, pages_t pages,
54 hvio_iommu_getmap(devhandle_t dev_hdl, tsbid_t tsbid, io_attributes_t *attr_p,
60 hvio_iommu_getbypass(devhandle_t dev_hdl, r_addr_t ra, io_attributes_t attr,
66 hvio_peek(devhandle_t dev_hdl, r_addr_t ra, size_t size, uint32_t *status,
72 hvio_poke(devhandle_t dev_hdl, r_addr_t ra, uint64_t sizes, uint64_t data,
78 hvio_dma_sync(devhandle_t dev_hdl, r_addr_t ra, size_t num_bytes,
84 hvio_msiq_conf(devhandle_t dev_hdl, msiqid_t msiq_id, r_addr_t ra,
90 hvio_msiq_info(devhandle_t dev_hdl, msiqid_t msiq_id, r_addr_t *r_addr_p,
96 hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id,
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H A Dpx_libhv.c48 static uint64_t hvio_rp_mps(devhandle_t dev_hdl, pci_device_t bdf, int32_t *mps,
52 hvio_get_rp_mps_cap(devhandle_t dev_hdl, pci_device_t bdf, int32_t *mps_cap) in hvio_get_rp_mps_cap()
58 hvio_set_rp_mps(devhandle_t dev_hdl, pci_device_t bdf, int32_t mps) in hvio_set_rp_mps()
64 hvio_rp_mps(devhandle_t dev_hdl, pci_device_t bdf, int32_t *mps, int op) in hvio_rp_mps()
H A Dpx_lib4v.c87 px_lib_dev_init(dev_info_t *dip, devhandle_t *dev_hdl) in px_lib_dev_init()
125 *dev_hdl = (devhandle_t)((rp->phys_addr >> 32) & DEVHDLE_MASK); in px_lib_dev_init()
646 devhandle_t hdl = DIP_TO_HANDLE(dip); /* need to cache hdl */ in px_lib_dma_sync()
/titanic_44/usr/src/uts/sun4u/io/px/
H A Dpx_lib4u.h305 extern uint64_t hvio_intr_devino_to_sysino(devhandle_t dev_hdl, pxu_t *pxu_p,
307 extern uint64_t hvio_intr_getvalid(devhandle_t dev_hdl, sysino_t sysino,
309 extern uint64_t hvio_intr_setvalid(devhandle_t dev_hdl, sysino_t sysino,
311 extern uint64_t hvio_intr_getstate(devhandle_t dev_hdl, sysino_t sysino,
313 extern uint64_t hvio_intr_setstate(devhandle_t dev_hdl, sysino_t sysino,
315 extern uint64_t hvio_intr_gettarget(devhandle_t dev_hdl, pxu_t *pxu_p,
317 extern uint64_t hvio_intr_settarget(devhandle_t dev_hdl, pxu_t *pxu_p,
320 extern uint64_t hvio_iommu_map(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid,
323 extern uint64_t hvio_iommu_demap(devhandle_t dev_hdl, pxu_t *pxu_p,
325 extern uint64_t hvio_iommu_getmap(devhandle_t dev_hdl, pxu_t *pxu_p,
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H A Dpx_hlib.c169 static uint64_t msiq_suspend(devhandle_t dev_hdl, pxu_t *pxu_p);
170 static void msiq_resume(devhandle_t dev_hdl, pxu_t *pxu_p);
1787 hvio_iommu_map(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid, pages_t pages, in hvio_iommu_map()
1853 hvio_iommu_demap(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid, in hvio_iommu_demap()
1882 hvio_iommu_getmap(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid, in hvio_iommu_getmap()
2026 hvio_iommu_getbypass(devhandle_t dev_hdl, pxu_t *pxu_p, r_addr_t ra, in hvio_iommu_getbypass()
2047 hvio_intr_devino_to_sysino(devhandle_t dev_hdl, pxu_t *pxu_p, devino_t devino, in hvio_intr_devino_to_sysino()
2065 hvio_intr_getvalid(devhandle_t dev_hdl, sysino_t sysino, in hvio_intr_getvalid()
2084 hvio_intr_setvalid(devhandle_t dev_hdl, sysino_t sysino, in hvio_intr_setvalid()
2108 hvio_intr_getstate(devhandle_t dev_hdl, sysino_t sysino, in hvio_intr_getstate()
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H A Dpx_lib4u.c179 px_lib_dev_init(dev_info_t *dip, devhandle_t *dev_hdl) in px_lib_dev_init()
280 *dev_hdl = (devhandle_t)csr_base; in px_lib_dev_init()
1327 devhandle_t dev_hdl, xbus_dev_hdl; in px_lib_suspend()
1332 dev_hdl = (devhandle_t)pxu_p->px_address[PX_REG_CSR]; in px_lib_suspend()
1333 xbus_dev_hdl = (devhandle_t)pxu_p->px_address[PX_REG_XBC]; in px_lib_suspend()
1355 devhandle_t dev_hdl, xbus_dev_hdl; in px_lib_resume()
1361 dev_hdl = (devhandle_t)pxu_p->px_address[PX_REG_CSR]; in px_lib_resume()
1362 xbus_dev_hdl = (devhandle_t)pxu_p->px_address[PX_REG_XBC]; in px_lib_resume()
/titanic_44/usr/src/uts/sun4v/io/fpc/
H A Dfpc-impl-4v.h38 typedef uint64_t devhandle_t; typedef
42 extern int fpc_get_fire_perfreg(devhandle_t dev_hdl, int regid, uint64_t *data);
43 extern int fpc_set_fire_perfreg(devhandle_t dev_hdl, int regid, uint64_t data);
H A Dfpc-impl-4v.c122 devhandle_t dev_hdl; in fpc_platform_node_init()
152 dev_hdl = (devhandle_t)((rp->phys_addr >> 32) & DEVHDLE_MASK); in fpc_platform_node_init()
243 devhandle_t dev_hdl = (devhandle_t)handle; in fpc_hv_perfreg_io()
H A Dfpc-asm-4v.s47 fpc_get_fire_perfreg(devhandle_t dev_hdl, int regid, uint64_t *data)
52 fpc_set_fire_perfreg(devhandle_t dev_hdl, int regid, uint64_t data)
/titanic_44/usr/src/uts/sun4v/sys/
H A Dpci_cfgacc_4v.h37 extern uint64_t hvio_config_get(devhandle_t, pci_device_t, pci_config_offset_t,
39 extern uint64_t hvio_config_put(devhandle_t, pci_device_t, pci_config_offset_t,
/titanic_44/usr/src/uts/sun4v/io/pciex/
H A Dpci_cfgacc_asm.s42 hvio_config_get(devhandle_t dev_hdl, pci_device_t bdf, pci_config_offset_t off,
48 hvio_config_put(devhandle_t dev_hdl, pci_device_t bdf, pci_config_offset_t off,
/titanic_44/usr/src/uts/sun4/io/px/
H A Dpx_ioapi.h66 typedef uint64_t devhandle_t; typedef
H A Dpx_var.h83 devhandle_t px_dev_hdl; /* device handle */
H A Dpx_lib.h57 extern int px_lib_dev_init(dev_info_t *dip, devhandle_t *dev_hdl);
H A Dpx.c229 devhandle_t dev_hdl = NULL; in px_attach()