Home
last modified time | relevance | path

Searched refs:dev_priv (Results 1 – 14 of 14) sorted by relevance

/titanic_44/usr/src/uts/intel/io/drm/
H A Dradeon_cp.c827 drm_radeon_private_t *dev_priv = dev->dev_private; in RADEON_READ_PLL() local
833 static int RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr) in RADEON_READ_PCIE() argument
840 static void radeon_status(drm_radeon_private_t *dev_priv) in radeon_status() argument
865 static int radeon_do_pixcache_flush(drm_radeon_private_t *dev_priv) in radeon_do_pixcache_flush() argument
870 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; in radeon_do_pixcache_flush()
876 for (i = 0; i < dev_priv->usec_timeout; i++) { in radeon_do_pixcache_flush()
886 radeon_status(dev_priv); in radeon_do_pixcache_flush()
891 static int radeon_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries) in radeon_do_wait_for_fifo() argument
895 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; in radeon_do_wait_for_fifo()
897 for (i = 0; i < dev_priv->usec_timeout; i++) { in radeon_do_wait_for_fifo()
[all …]
H A Di915_irq.c66 igdng_enable_irq(drm_i915_private_t *dev_priv, u32 mask, int gfx_irq) in igdng_enable_irq() argument
68 if (gfx_irq && ((dev_priv->gt_irq_mask_reg & mask) != 0)) { in igdng_enable_irq()
69 dev_priv->gt_irq_mask_reg &= ~mask; in igdng_enable_irq()
70 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); in igdng_enable_irq()
72 } else if ((dev_priv->irq_mask_reg & mask) != 0) { in igdng_enable_irq()
73 dev_priv->irq_mask_reg &= ~mask; in igdng_enable_irq()
74 I915_WRITE(DEIMR, dev_priv->irq_mask_reg); in igdng_enable_irq()
81 igdng_disable_irq(drm_i915_private_t *dev_priv, u32 mask, int gfx_irq) in igdng_disable_irq() argument
83 if (gfx_irq && ((dev_priv->gt_irq_mask_reg & mask) != mask)) { in igdng_disable_irq()
84 dev_priv->gt_irq_mask_reg |= mask; in igdng_disable_irq()
[all …]
H A Di915_dma.c52 drm_i915_private_t *dev_priv = dev->dev_private; in i915_wait_ring() local
53 drm_i915_ring_buffer_t *ring = &(dev_priv->ring); in i915_wait_ring()
85 drm_i915_private_t *dev_priv = dev->dev_private; in i915_init_hardware_status() local
96 dev_priv->status_page_dmah = dmah; in i915_init_hardware_status()
97 dev_priv->hw_status_page = (void *)dmah->vaddr; in i915_init_hardware_status()
98 dev_priv->dma_status_page = dmah->paddr; in i915_init_hardware_status()
100 (void) memset(dev_priv->hw_status_page, 0, PAGE_SIZE); in i915_init_hardware_status()
102 I915_WRITE(HWS_PGA, dev_priv->dma_status_page); in i915_init_hardware_status()
105 …d hardware status page add 0x%lx read GEM HWS 0x%x\n",dev_priv->hw_status_page, READ_HWSP(dev_priv… in i915_init_hardware_status()
111 drm_i915_private_t *dev_priv = dev->dev_private; in i915_free_hardware_status() local
[all …]
H A Dradeon_irq.c44 radeon_acknowledge_irqs(drm_radeon_private_t *dev_priv, u32 mask) in radeon_acknowledge_irqs() argument
75 drm_radeon_private_t *dev_priv = in radeon_driver_irq_handler() local
83 stat = radeon_acknowledge_irqs(dev_priv, (RADEON_SW_INT_TEST_ACK | in radeon_driver_irq_handler()
88 stat &= dev_priv->irq_enable_reg; in radeon_driver_irq_handler()
92 DRM_WAKEUP(&dev_priv->swi_queue); in radeon_driver_irq_handler()
97 int vblank_crtc = dev_priv->vblank_crtc; in radeon_driver_irq_handler()
121 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_emit_irq() local
125 atomic_inc(&dev_priv->swi_emitted); in radeon_emit_irq()
126 ret = atomic_read(&dev_priv->swi_emitted); in radeon_emit_irq()
139 drm_radeon_private_t *dev_priv = in radeon_wait_irq() local
[all …]
H A Dradeon_state.c49 radeon_check_and_fixup_offset(drm_radeon_private_t *dev_priv, in radeon_check_and_fixup_offset() argument
53 u32 fb_end = dev_priv->fb_location + dev_priv->fb_size - 1; in radeon_check_and_fixup_offset()
76 if (RADEON_CHECK_OFFSET(dev_priv, off)) in radeon_check_and_fixup_offset()
84 if (off < (dev_priv->fb_size + dev_priv->gart_size)) { in radeon_check_and_fixup_offset()
91 off = off - fb_end - 1 + dev_priv->gart_vm_start; in radeon_check_and_fixup_offset()
94 if (RADEON_CHECK_OFFSET(dev_priv, off)) { in radeon_check_and_fixup_offset()
103 radeon_check_and_fixup_packets(drm_radeon_private_t *dev_priv, in radeon_check_and_fixup_packets() argument
109 if (radeon_check_and_fixup_offset(dev_priv, filp_priv, in radeon_check_and_fixup_packets()
117 if (radeon_check_and_fixup_offset(dev_priv, filp_priv, in radeon_check_and_fixup_packets()
130 if (radeon_check_and_fixup_offset(dev_priv, filp_priv, in radeon_check_and_fixup_packets()
[all …]
H A Di915_gem.c84 drm_i915_private_t *dev_priv = dev->dev_private; in i915_gem_init_ioctl() local
105 (void) drm_mm_init(&dev_priv->mm.gtt_space, in i915_gem_init_ioctl()
107 …total %x, dev_priv->mm.gtt_space 0x%x gtt_start 0x%lx", dev->gtt_total, dev_priv->mm.gtt_space, ar… in i915_gem_init_ioctl()
535 drm_i915_private_t *dev_priv = dev->dev_private; in i915_gem_object_move_to_active() local
545 &dev_priv->mm.active_list, (caddr_t)obj_priv); in i915_gem_object_move_to_active()
553 drm_i915_private_t *dev_priv = dev->dev_private; in i915_gem_object_move_to_flushing() local
556 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list, (caddr_t)obj_priv); in i915_gem_object_move_to_flushing()
564 drm_i915_private_t *dev_priv = dev->dev_private; in i915_gem_object_move_to_inactive() local
571 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list, (caddr_t)obj_priv); in i915_gem_object_move_to_inactive()
591 drm_i915_private_t *dev_priv = dev->dev_private; in i915_add_request() local
[all …]
H A Dr300_cmdbuf.c64 static int r300_emit_cliprects(drm_radeon_private_t *dev_priv, in r300_emit_cliprects() argument
260 r300_emit_carefully_checked_packet0(drm_radeon_private_t *dev_priv, in r300_emit_carefully_checked_packet0() argument
283 if (!RADEON_CHECK_OFFSET(dev_priv, (u32) values[i])) { in r300_emit_carefully_checked_packet0()
313 static __inline__ int r300_emit_packet0(drm_radeon_private_t *dev_priv, in r300_emit_packet0() argument
338 return (r300_emit_carefully_checked_packet0(dev_priv, in r300_emit_packet0()
362 static inline int r300_emit_vpu(drm_radeon_private_t *dev_priv, in r300_emit_vpu() argument
400 static inline int r300_emit_clear(drm_radeon_private_t *dev_priv, in r300_emit_clear() argument
421 static inline int r300_emit_3d_load_vbpntr(drm_radeon_private_t *dev_priv, in r300_emit_3d_load_vbpntr() argument
447 if (!RADEON_CHECK_OFFSET(dev_priv, payload[i])) { in r300_emit_3d_load_vbpntr()
458 if (!RADEON_CHECK_OFFSET(dev_priv, payload[i])) { in r300_emit_3d_load_vbpntr()
[all …]
H A Dradeon_drv.h160 #define GET_RING_HEAD(dev_priv) \ argument
161 (dev_priv->writeback_works ? \
162 DRM_READ32((dev_priv)->ring_rptr, 0) : \
165 #define SET_RING_HEAD(dev_priv, val) \ argument
166 DRM_WRITE32((dev_priv)->ring_rptr, 0, (val))
333 #define RADEON_CHECK_OFFSET(dev_priv, off) \ argument
334 (((off >= dev_priv->fb_location) && \
335 (off <= (dev_priv->fb_location + dev_priv->fb_size - 1))) || \
336 ((off >= dev_priv->gart_vm_start) && \
337 (off <= (dev_priv->gart_vm_start + dev_priv->gart_size - 1))))
[all …]
H A Di915_mem.c58 drm_i915_private_t *dev_priv = dev->dev_private; in mark_block() local
59 drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv; in mark_block()
67 shift = dev_priv->tex_lru_log_granularity; in mark_block()
278 struct mem_block **get_heap(drm_i915_private_t * dev_priv, int region) in get_heap() argument
282 return (&dev_priv->agp_heap); in get_heap()
294 drm_i915_private_t *dev_priv = dev->dev_private; in i915_mem_alloc() local
298 if (!dev_priv) { in i915_mem_alloc()
314 heap = get_heap(dev_priv, alloc.region); in i915_mem_alloc()
343 drm_i915_private_t *dev_priv = dev->dev_private; in i915_mem_free() local
347 if (!dev_priv) { in i915_mem_free()
[all …]
H A Di915_gem_tiling.c98 drm_i915_private_t *dev_priv = dev->dev_private; in i915_gem_detect_bit_6_swizzle() local
187 dev_priv->mm.bit_6_swizzle_x = swizzle_x; in i915_gem_detect_bit_6_swizzle()
188 dev_priv->mm.bit_6_swizzle_y = swizzle_y; in i915_gem_detect_bit_6_swizzle()
272 drm_i915_private_t *dev_priv = dev->dev_private; in i915_gem_set_tiling() local
300 args.swizzle_mode = dev_priv->mm.bit_6_swizzle_x; in i915_gem_set_tiling()
302 args.swizzle_mode = dev_priv->mm.bit_6_swizzle_y; in i915_gem_set_tiling()
347 drm_i915_private_t *dev_priv = dev->dev_private; in i915_gem_get_tiling() local
368 args.swizzle_mode = dev_priv->mm.bit_6_swizzle_x; in i915_gem_get_tiling()
371 args.swizzle_mode = dev_priv->mm.bit_6_swizzle_y; in i915_gem_get_tiling()
H A Dradeon_mem.c228 get_heap(drm_radeon_private_t *dev_priv, int region) in get_heap() argument
232 return (&dev_priv->gart_heap); in get_heap()
234 return (&dev_priv->fb_heap); in get_heap()
245 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_mem_alloc() local
249 if (!dev_priv) { in radeon_mem_alloc()
271 heap = get_heap(dev_priv, alloc.region); in radeon_mem_alloc()
301 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_mem_free() local
305 if (!dev_priv) { in radeon_mem_free()
312 heap = get_heap(dev_priv, memfree.region); in radeon_mem_free()
332 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_mem_init_heap() local
[all …]
H A Di915_drv.h572 #define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg))
573 #define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
574 #define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg))
575 #define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val))
607 DRM_DEBUG("dev_priv->ring.virtual_start (%lx)\n", (dev_priv->ring.virtual_start)); \
609 if (dev_priv->ring.space < (n)*4) \
612 outring = dev_priv->ring.tail; \
613 ringmask = dev_priv->ring.tail_mask; \
614 virt = dev_priv->ring.virtual_start; \
619 if (dev_priv->ring.space < (n)*4) \
[all …]
/titanic_44/usr/src/uts/common/inet/
H A Dinetddi.c110 static struct dev_priv { struct
137 ndevs = sizeof (netdev_privs) / sizeof (struct dev_priv); in inet_attach() argument
/titanic_44/usr/src/uts/common/io/drm/
H A DdrmP.h274 dev_priv->sarea = map; \