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Searched refs:cpu_phase (Results 1 – 1 of 1) sorted by relevance

/titanic_44/usr/src/uts/i86xpv/os/
H A Dmp_xen.c132 static int cpu_phase[NCPU]; variable
514 cpu_phase[CPU->cpu_id] = CPU_PHASE_SAFE; in enter_safe_phase()
515 while (cpu_phase[CPU->cpu_id] == CPU_PHASE_SAFE) in enter_safe_phase()
535 if (cpu_phase[CPU->cpu_id] == CPU_PHASE_WAIT_SAFE) in mach_cpu_idle()
551 if (cpu_phase[CPU->cpu_id] == CPU_PHASE_WAIT_SAFE) in mach_cpu_pause()
606 switch (cpu_phase[i]) { in mp_enter_barrier()
608 cpu_phase[i] = CPU_PHASE_WAIT_SAFE; in mp_enter_barrier()
642 switch (cpu_phase[i]) { in mp_leave_barrier()
660 cpu_phase[i] = CPU_PHASE_NONE; in mp_leave_barrier()
680 ASSERT(cpu_phase[cp->cpu_id] == CPU_PHASE_SAFE); in poweroff_vcpu()
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