| /titanic_44/usr/src/uts/sun4/os/ |
| H A D | x_call.c | 239 xt_one(int cix, xcfunc_t *func, uint64_t arg1, uint64_t arg2) in xt_one() argument
241 if (!CPU_IN_SET(cpu_ready_set, cix)) { in xt_one()
244 xt_one_unchecked(cix, func, arg1, arg2); in xt_one()
252 xt_one_unchecked(int cix, xcfunc_t *func, uint64_t arg1, uint64_t arg2) in xt_one_unchecked() argument
274 CPUSET_ADD(tset, cix); in xt_one_unchecked()
276 if (cix == lcx) { in xt_one_unchecked()
289 send_one_mondo(cix); in xt_one_unchecked()
421 xc_one(int cix, xcfunc_t *func, uint64_t arg1, uint64_t arg2) in xc_one() argument
432 if (!CPU_IN_SET(cpu_ready_set, cix)) in xc_one()
444 CPUSET_ADD(tset, cix); in xc_one()
[all …]
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| /titanic_44/usr/src/uts/common/io/ |
| H A D | avintr.c | 519 int cpu_in_chain, cix; in wait_till_seen() local
526 for (cix = 0; cix < NCPU; cix++) { in wait_till_seen()
527 cpup = cpu[cix]; in wait_till_seen()
528 if (cpup != NULL && CPU_IN_SET(cpus_to_check, cix)) { in wait_till_seen()
532 CPUSET_DEL(cpus_to_check, cix); in wait_till_seen()
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| /titanic_44/usr/src/uts/i86pc/io/dr/ |
| H A D | dr_cpu.c | 355 int c, cix, i, lastoffline = -1, rv = 0; in dr_pre_release_cpu() local
370 cix = dr_cpu_status(hp, devset, ds); in dr_pre_release_cpu()
388 for (c = 0; c < cix; c++) { in dr_pre_release_cpu()
398 if (c < cix) in dr_pre_release_cpu()
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| /titanic_44/usr/src/uts/sun4u/ngdr/io/ |
| H A D | dr_cpu.c | 424 int c, cix, i, lastoffline = -1, rv = 0; in dr_pre_release_cpu() local
439 cix = dr_cpu_status(hp, devset, ds); in dr_pre_release_cpu()
455 for (c = 0; c < cix; c++) { in dr_pre_release_cpu()
465 if (c < cix) in dr_pre_release_cpu()
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| /titanic_44/usr/src/uts/common/io/ath/ |
| H A D | ath_main.c | 677 uint8_t rix, cix, txrate, ctsrate; in ath_tx_start() local
854 cix = rt->info[rix].controlRate; in ath_tx_start()
855 ctsrate = rt->info[cix].rateCode; in ath_tx_start()
857 ctsrate |= rt->info[cix].shortPreamble; in ath_tx_start()
866 rt, IEEE80211_ACK_SIZE, cix, shortPreamble); in ath_tx_start()
873 rt, IEEE80211_ACK_SIZE, cix, shortPreamble); in ath_tx_start()
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| /titanic_44/usr/src/uts/common/io/arn/ |
| H A D | arn_xmit.c | 1346 uint8_t rix = 0, cix, ctsrate = 0; in ath_buf_set_rate() local
1369 cix = rt->info[rix].ctrl_rate; in ath_buf_set_rate()
1384 cix = rt->info[sc->sc_protrix].ctrl_rate; in ath_buf_set_rate()
1403 cix = rt->info[sc->sc_protrix].ctrl_rate; in ath_buf_set_rate()
1416 ctsrate = rt->info[cix].ratecode | in ath_buf_set_rate()
1417 (bf_isshpreamble(bf) ? rt->info[cix].short_preamble : 0); in ath_buf_set_rate()
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| H A D | arn_rc.c | 1748 uint8_t cix = rate_table->info[i].ctrl_rate; in arn_setup_rate_table() local
1757 cix, in arn_setup_rate_table()
1762 cix, in arn_setup_rate_table()
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| /titanic_44/usr/src/uts/sun4u/io/ |
| H A D | sbd.c | 3982 int c, cix; in sbd_cpu_cnt() local
3992 for (c = cix = 0; c < MAX_CMP_UNITS_PER_BOARD; c++) { in sbd_cpu_cnt()
4013 cix++; in sbd_cpu_cnt()
4016 return (cix); in sbd_cpu_cnt()
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