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/titanic_44/usr/src/cmd/fm/eversholt/files/sparc/sun4v/
H A Dgcpu.esc53 * some set of @chip, @core, and @strand resources since this is
56 * cache per chip, another may have an L2 per core.
87 ERPT_EVENT(chip, itlb-uc);
90 ERPT_EVENT(chip, dtlb-uc);
93 ERPT_EVENT(chip, icache-uc);
95 ERPT_EVENT(chip, dcache-uc);
97 ERPT_EVENT(chip, ireg-uc);
100 ERPT_EVENT(chip, freg-uc);
103 ERPT_EVENT(chip, mreg-uc);
106 ERPT_EVENT(chip, l2data-uc);
[all …]
H A Dzambezi.esc86 asru chip;
94 event error.cpu.ultraSPARC-T2plus.opu.protocol@chip;
95 event error.cpu.ultraSPARC-T2plus.lfu-c.chip@chip;
96 event error.cpu.ultraSPARC-T2plus.lfu-f.chip@chip;
97 event error.cpu.ultraSPARC-T2plus.lfu-u.chip@chip;
98 event error.cpu.ultraSPARC-T2plus.gpd-u.chip@chip;
99 event error.cpu.ultraSPARC-T2plus.gpd-c.chip@chip;
100 event error.cpu.ultraSPARC-T2plus.asu.protocol@chip;
102 event fault.cpu.ultraSPARC-T2plus.chip@chip
103 FITrate=CPU_CHIP_FIT, ASRU=chip, FRU=cpuboard;
[all …]
/titanic_44/usr/src/lib/fm/topo/modules/sun4u/chip/
H A Dchip_sun4u.c61 typedef struct chip { struct
78 chip_t *chip; in _topo_init() local
84 if ((chip = topo_mod_zalloc(mod, sizeof (chip_t))) == NULL) in _topo_init()
87 if ((chip->chip_kc = kstat_open()) == NULL) { in _topo_init()
90 topo_mod_free(mod, chip, sizeof (chip_t)); in _topo_init()
94 chip->chip_ncpustats = sysconf(_SC_CPUID_MAX); in _topo_init()
95 if ((chip->chip_cpustats = topo_mod_zalloc(mod, ( in _topo_init()
96 chip->chip_ncpustats + 1) * sizeof (kstat_t *))) == NULL) { in _topo_init()
97 (void) kstat_close(chip->chip_kc); in _topo_init()
98 topo_mod_free(mod, chip, sizeof (chip_t)); in _topo_init()
[all …]
H A DMakefile31 include ../../sun4/chip/Makefile.chip
/titanic_44/usr/src/cmd/fm/eversholt/files/i386/i86pc/
H A Dintel.esc37 event ereport.cpu.intel.leafclass@chip/core/strand { within(t) }
56 engine serd.cpu.intel.simple@chip/core/strand, N=3, T=72h;
57 event fault.cpu.intel.internal@chip/core/strand,
58 engine=serd.cpu.intel.simple@chip/core/strand;
60 prop fault.cpu.intel.internal@chip/core/strand
62 ereport.cpu.intel.microcode_rom_parity@chip/core/strand,
63 ereport.cpu.intel.internal_timer@chip/core/strand,
64 ereport.cpu.intel.internal_parity@chip/core/strand,
65 ereport.cpu.intel.unclassified@chip/core/strand,
66 ereport.cpu.intel.frc@chip/core/strand;
[all …]
H A Damd64.esc57 * "prop foo@chip/memory-controller/dimm/rank -> blah@chip/core/strand"
61 * all dimms, ranks and cpus on the same chip (since chip appears in the
66 asru(chip/memory-controller/dimm/rank)) \
68 asru(chip/memory-controller/dimm)))
122 event ereport.cpu.amd.ic.inf_sys_ecc1@chip/core/strand{within(5s)};
123 event ereport.cpu.amd.dc.inf_sys_ecc1@chip/core/strand{within(5s)};
124 event ereport.cpu.amd.bu.s_ecc1@chip/core/strand{within(5s)};
125 event ereport.cpu.amd.nb.mem_ce@chip/core/strand{within(5s)};
145 engine stat.sbpgflt@chip/memory-controller/dimm/rank;
146 engine stat.ckpgflt@chip/memory-controller/dimm/rank;
[all …]
H A Dgcpu.esc44 event ereport.cpu.generic-x86.leafclass@chip/core/strand { within(1s) }
63 engine serd.cpu.generic-x86.simple@chip/core/strand, N=SMPL_N, T=72h;
64 event fault.cpu.generic-x86.internal@chip/core/strand,
65 engine=serd.cpu.generic-x86.simple@chip/core/strand;
67 prop fault.cpu.generic-x86.internal@chip/core/strand
70 ereport.cpu.generic-x86.microcode_rom_parity@chip/core/strand,
71 ereport.cpu.generic-x86.internal_timer@chip/core/strand,
72 ereport.cpu.generic-x86.internal_parity@chip/core/strand,
73 ereport.cpu.generic-x86.unclassified@chip/core/strand,
74 ereport.cpu.generic-x86.internal_unclassified@chip/core/strand,
[all …]
H A Dgcpu_amd.esc28 * Eversholt rules for generic AMD with on-chip memory-controller(s), as seen
32 * are observed via MCA (typically through an on-chip memory-controller)
44 * those chip versions that include an Online Spare Control register; this
45 * register provides counts of ECC errors seen per channel and chip-select
47 * hc:///motherboard/chip/memory-controller/dram-channel/chip-select
54 * The number of pages that must be faulted on a chip-select for repeated
62 * chip-select (must be at least CS_PAGEFLT_THRESH). If a chip-select
70 * correctable ereports are experienced on a single chip-select within
77 #define CSPATH chip/memory-controller/dram-channel/chip-select
86 * members matches the chip-select path. This is used to constrain
[all …]
/titanic_44/usr/src/lib/fm/topo/modules/sun4v/platform-cpu/
H A Dcpu_mdesc.c47 cpu_find_proc(md_info_t *chip, uint32_t procid) { in cpu_find_proc() argument
52 for (i = 0, procp = chip->procs; i < chip->nprocs; i++, procp++) { in cpu_find_proc()
62 cpu_find_cpumap(md_info_t *chip, uint32_t cpuid) { in cpu_find_cpumap() argument
66 for (i = 0, mcmp = chip->cpus; i < chip->ncpus; i++, mcmp++) { in cpu_find_cpumap()
75 cpu_get_serialid_mdesc(md_info_t *chip, uint32_t cpuid, uint64_t *serialidp) in cpu_get_serialid_mdesc() argument
78 if ((mcmp = cpu_find_cpumap(chip, cpuid)) != NULL) { in cpu_get_serialid_mdesc()
86 cpu_n1_mdesc_init(topo_mod_t *mod, md_t *mdp, md_info_t *chip) in cpu_n1_mdesc_init() argument
96 chip->ncpus = md_scan_dag(mdp, in cpu_n1_mdesc_init()
101 topo_mod_dprintf(mod, "Found %d cpus\n", chip->ncpus); in cpu_n1_mdesc_init()
103 chip->cpus = topo_mod_zalloc(mod, chip->ncpus * sizeof (md_cpumap_t)); in cpu_n1_mdesc_init()
[all …]
H A Dcpu.c121 md_info_t *chip; in _topo_init() local
128 if ((chip = topo_mod_zalloc(mod, sizeof (md_info_t))) == NULL) in _topo_init()
131 if (cpu_mdesc_init(mod, chip) != 0) { in _topo_init()
133 topo_mod_free(mod, chip, sizeof (md_info_t)); in _topo_init()
137 topo_mod_setspecific(mod, (void *)chip); in _topo_init()
142 cpu_mdesc_fini(mod, chip); in _topo_init()
143 topo_mod_free(mod, chip, sizeof (md_info_t)); in _topo_init()
155 md_info_t *chip; in _topo_fini() local
157 chip = (md_info_t *)topo_mod_getspecific(mod); in _topo_fini()
159 cpu_mdesc_fini(mod, chip); in _topo_fini()
[all …]
H A Dcpu_mdesc.h86 extern int cpu_mdesc_init(topo_mod_t *mod, md_info_t *chip);
87 extern void cpu_mdesc_fini(topo_mod_t *mod, md_info_t *chip);
89 extern int cpu_get_serialid_mdesc(md_info_t *chip, uint32_t cpuid,
91 extern md_cpumap_t *cpu_find_cpumap(md_info_t *chip, uint32_t cpuid);
92 extern md_proc_t *cpu_find_proc(md_info_t *chip, uint32_t procid);
/titanic_44/usr/src/uts/common/io/vr/
H A Dvr.c422 if (vrp->chip.state == CHIPSTATE_RUNNING) in vr_detach()
532 if (vrp->chip.state == CHIPSTATE_SUSPENDED_RUNNING) in vr_resume()
548 if (vrp->chip.state == CHIPSTATE_RUNNING) { in vr_suspend()
550 vrp->chip.state = CHIPSTATE_SUSPENDED_RUNNING; in vr_suspend()
630 vrp->chip.vendor = VR_GET16(vrp->acc_cfg, PCI_CONF_VENID); in vr_bus_config()
631 vrp->chip.device = VR_GET16(vrp->acc_cfg, PCI_CONF_DEVID); in vr_bus_config()
632 vrp->chip.revision = VR_GET16(vrp->acc_cfg, PCI_CONF_REVID); in vr_bus_config()
639 if (vrp->chip.revision >= vr_chip_info[n].revmin && in vr_bus_config()
640 vrp->chip.revision <= vr_chip_info[n].revmax) { in vr_bus_config()
642 (void*)&vrp->chip.info, in vr_bus_config()
[all …]
/titanic_44/usr/src/cmd/psrinfo/
H A Dpsrinfo.c228 struct pchip *chip; in print_vp() local
235 chip = l1->l_ptr; in print_vp()
237 if ((nspec != 0) && (chip->p_doit == 0)) in print_vp()
240 vcpu = chip->p_vcpus->l_ptr; in print_vp()
247 if ((chip->p_ncore == 1) || (chip->p_ncore == chip->p_nvcpu)) { in print_vp()
250 chip->p_nvcpu, in print_vp()
251 chip->p_nvcpu > 1 ? in print_vp()
257 chip->p_ncore, _("cores"), in print_vp()
258 chip->p_nvcpu, in print_vp()
259 chip->p_nvcpu > 1 ? in print_vp()
[all …]
/titanic_44/usr/src/lib/fm/topo/modules/sun4v/chip/
H A Dchip_sun4v.c77 md_info_t *chip; in _topo_init() local
83 if ((chip = topo_mod_zalloc(mod, sizeof (md_info_t))) == NULL) in _topo_init()
86 if (cpu_mdesc_init(mod, chip) != 0) { in _topo_init()
88 topo_mod_free(mod, chip, sizeof (md_info_t)); in _topo_init()
92 topo_mod_setspecific(mod, (void *)chip); in _topo_init()
97 cpu_mdesc_fini(mod, chip); in _topo_init()
98 topo_mod_free(mod, chip, sizeof (md_info_t)); in _topo_init()
110 md_info_t *chip; in _topo_fini() local
112 chip = (md_info_t *)topo_mod_getspecific(mod); in _topo_fini()
114 cpu_mdesc_fini(mod, chip); in _topo_fini()
[all …]
/titanic_44/usr/src/lib/fm/topo/modules/i86pc/chip/
H A Dchip_label.c177 tnode_t *chip; in simple_dimm_label_mp() local
212 chip = topo_node_parent(topo_node_parent(node)); in simple_dimm_label_mp()
216 (void) snprintf(buf, BUFSZ, fmtstr, topo_node_instance(chip), in simple_dimm_label_mp()
220 (void) snprintf(buf, BUFSZ, fmtstr, topo_node_instance(chip), in simple_dimm_label_mp()
221 (((topo_node_instance(chip) + 1) * dimms_per_chip) in simple_dimm_label_mp()
266 tnode_t *chip; in seq_dimm_label() local
292 chip = topo_node_parent(topo_node_parent(node)); in seq_dimm_label()
297 + (topo_node_instance(chip) * 4) + offset)); in seq_dimm_label()
301 (((topo_node_instance(chip) + 1) * 4) in seq_dimm_label()
671 tnode_t *chip, *chan; in simple_cs_label_mp() local
[all …]
H A Dchip.c459 tnode_t *chip; in create_chip() local
509 if ((chip = topo_node_lookup(pnode, CHIP_NODE_NAME, chipid)) == NULL) { in create_chip()
510 if ((chip = create_node(mod, pnode, auth, CHIP_NODE_NAME, in create_chip()
518 if (topo_method_register(mod, chip, chip_methods) < 0) in create_chip()
523 (void) topo_pgroup_create(chip, &chip_pgroup, &err); in create_chip()
524 nerr -= add_nvlist_strprop(mod, chip, cpu, PGNAME(CHIP), in create_chip()
526 nerr -= add_nvlist_longprops(mod, chip, cpu, PGNAME(CHIP), in create_chip()
540 if (topo_node_resource(chip, &fmri, &perr) != 0) in create_chip()
544 (void) topo_node_fru_set(chip, NULL, 0, &perr); in create_chip()
550 if (topo_node_fru_set(chip, fmri, 0, &perr) in create_chip()
[all …]
H A DMakefile26 MODULE = chip
29 MODULESRCS = chip.c chip_label.c chip_subr.c chip_amd.c chip_intel.c\
/titanic_44/usr/src/uts/intel/io/intel_nhm/
H A Dintel_nhmdrv.c117 int chip; in inhm_mc_ioctl() local
124 chip = getminor(dev) % MAX_CPU_NODES; in inhm_mc_ioctl()
125 if (inhm_mc_nvl[chip] == NULL || in inhm_mc_ioctl()
131 if (inhm_mc_nvl[chip]) in inhm_mc_ioctl()
133 inhm_create_nvl(chip); in inhm_mc_ioctl()
139 mcs.mcs_size = (uint32_t)inhm_mc_snapshotsz[chip]; in inhm_mc_ioctl()
147 if (ddi_copyout(inhm_mc_snapshot[chip], (void *)arg, in inhm_mc_ioctl()
148 inhm_mc_snapshotsz[chip], mode) < 0) in inhm_mc_ioctl()
/titanic_44/usr/src/cmd/fm/dicts/
H A DSUN4V.dict85 fault.cpu.ultraSPARC-T2plus.chip=57
86 fault.asic.ultraSPARC-T2plus.interconnect.lfu-c fault.cpu.ultraSPARC-T2plus.chip=58
87 fault.asic.ultraSPARC-T2plus.interconnect.lfu-f fault.cpu.ultraSPARC-T2plus.chip=59
88 fault.asic.ultraSPARC-T2plus.interconnect.lfu-u fault.cpu.ultraSPARC-T2plus.chip=60
90 fault.asic.ultraSPARC-T2plus.interconnect.gpd-u fault.cpu.ultraSPARC-T2plus.chip=62
91 fault.asic.ultraSPARC-T2plus.interconnect.gpd-c fault.cpu.ultraSPARC-T2plus.chip=63
106 fault.cpu.generic-sparc.chip=78
107 fault.cpu.generic-sparc.chip-nr=79
108 fault.cpu.generic-sparc.chip-uc=80
109 fault.cpu.generic-sparc.chip-uc-nr=81
H A DSCF.po37 msgstr "A fatal clock distribution error was detected by an ASIC or a CPU chip.\n Refer to %s for …
53 msgstr "A Clock chip has detected a lack of connectivity between the base cabinet and the expansion…
69 msgstr "A fatal error was detected within a Clock chip.\n Refer to %s for more information."
85 …ng poweron self-test, either within a Clock chip with within one of the external\ninterfaces of a …
101 msgstr "An internal fatal error within a CPU chip was detected.\n Refer to %s for more information…
103 msgstr "The domain using this CPU will be reset and the CPU chip will be deconfigured.\n"
105 msgstr "The CPU chip will be deconfigured after the domain is reset.\n"
117 msgstr "An internal fatal error within a core on a CPU chip was detected.\n Refer to %s for more i…
121 msgstr "The domain using this CPU chip is reset.\n"
133 msgstr "An internal fatal error within a strand on a CPU chip was detected.\n Refer to %s for more…
[all …]
/titanic_44/usr/src/uts/sun4u/sys/
H A Dopl_cfg.h60 #define OPL_PORTID(board, chip) ((1 << 10) | (board << 5) | (chip << 3)) argument
62 #define OPL_CPUID(board, chip, core, cpu) \ argument
64 ((board << 5) | (chip << 3) | (core << 1) | (cpu))
69 #define OPL_PROC_AS(board, chip) \ argument
72 (1ULL << 33) | ((uint64_t)chip << 4))
/titanic_44/usr/src/uts/common/io/fibre-channel/fca/qlc/
H A Dql_hba_fru.c236 uint16_t chip = ha->device_id; in ql_populate_hba_fru_details() local
336 switch (chip & 0xFF00) { in ql_populate_hba_fru_details()
416 switch (chip & 0xFF00) { in ql_populate_hba_fru_details()
436 "%x", chip); in ql_populate_hba_fru_details()
438 FCHBA_MODEL_DESCRIPTION_LEN, "%x", chip); in ql_populate_hba_fru_details()
465 "%x", chip); in ql_populate_hba_fru_details()
467 FCHBA_MODEL_DESCRIPTION_LEN, "%x", chip); in ql_populate_hba_fru_details()
/titanic_44/usr/src/uts/common/io/rge/
H A Drge_chip.c697 chip_id_t *chip = &rgep->chipid; in rge_chip_ident() local
706 chip->mac_ver = val32; in rge_chip_ident()
707 chip->is_pcie = pci_lcap_locate(rgep->cfg_handle, in rge_chip_ident()
713 chip->enable_mac_first = !chip->is_pcie; in rge_chip_ident()
714 if (chip->mac_ver == MAC_VER_8101E_C) { in rge_chip_ident()
715 chip->is_pcie = B_FALSE; in rge_chip_ident()
723 chip->phy_ver = val16; in rge_chip_ident()
726 if (chip->mac_ver == MAC_VER_8169 || in rge_chip_ident()
727 chip->mac_ver == MAC_VER_8169S_D || in rge_chip_ident()
728 chip->mac_ver == MAC_VER_8169S_E || in rge_chip_ident()
[all …]
/titanic_44/usr/src/uts/sun4u/tazmo/io/
H A Denvctrl.c2895 struct envctrl_pcf8574_chip chip; in envctrl_set_fsp() local
2899 chip.val = ENVCTRL_FSP_OFF; /* init all values to off */ in envctrl_set_fsp()
2900 chip.chip_num = ENVCTRL_PCF8574_DEV6; /* 0x01 port 1 */ in envctrl_set_fsp()
2901 chip.type = PCF8574A; in envctrl_set_fsp()
2906 chip.val = (~(ENVCTRL_FSP_KEYMASK | ENVCTRL_FSP_POMASK) & (*val)); in envctrl_set_fsp()
2908 chip.val = ~chip.val; in envctrl_set_fsp()
2909 (void) envctrl_xmit(unitp, (caddr_t *)(void *)&chip, PCF8574); in envctrl_set_fsp()
2914 envctrl_get_dskled(struct envctrlunit *unitp, struct envctrl_pcf8574_chip *chip) in envctrl_get_dskled() argument
2920 if (chip->chip_num > ENVCTRL_PCF8574_DEV2 || in envctrl_get_dskled()
2921 chip->type != ENVCTRL_ENCL_BACKPLANE4 && in envctrl_get_dskled()
[all …]
/titanic_44/usr/src/lib/libdtrace/common/
H A Dsched.d75 inline chipid_t chip = curcpu->cpu_chip; variable
76 #pragma D attributes Stable/Stable/Common chip
77 #pragma D binding "1.0" chip

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