| /titanic_44/usr/src/uts/common/io/xge/hal/xgehal/ |
| H A D | xgehal-channel.c | 39 xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; in __hal_channel_dtr_next_reservelist() local
41 if (channel->reserve_top >= channel->reserve_length) { in __hal_channel_dtr_next_reservelist()
45 *dtrh = channel->reserve_arr[channel->reserve_top++]; in __hal_channel_dtr_next_reservelist()
58 xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; in __hal_channel_dtr_next_freelist() local
60 if (channel->reserve_initial == channel->free_length) { in __hal_channel_dtr_next_freelist()
64 *dtrh = channel->free_arr[channel->free_length++]; in __hal_channel_dtr_next_freelist()
100 xge_hal_channel_t *channel; in __hal_channel_allocate() local
122 channel = (xge_hal_channel_t *) xge_os_malloc(hldev->pdev, size); in __hal_channel_allocate()
123 if (channel == NULL) { in __hal_channel_allocate()
126 xge_os_memzero(channel, size); in __hal_channel_allocate()
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| H A D | xgehal-channel-fp.c | 32 xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; in __hal_channel_dtr_alloc() local
36 if (channel->terminating) { in __hal_channel_dtr_alloc()
40 if (channel->reserve_length - channel->reserve_top > in __hal_channel_dtr_alloc()
41 channel->reserve_threshold) { in __hal_channel_dtr_alloc()
44 *dtrh = channel->reserve_arr[--channel->reserve_length]; in __hal_channel_dtr_alloc()
49 channel->type, channel->post_qid, in __hal_channel_dtr_alloc()
50 channel->compl_qid, channel->reserve_length); in __hal_channel_dtr_alloc()
56 xge_os_spin_lock_irq(&channel->free_lock, flags); in __hal_channel_dtr_alloc()
58 xge_os_spin_lock(&channel->free_lock); in __hal_channel_dtr_alloc()
67 if (channel->reserve_initial - channel->free_length > in __hal_channel_dtr_alloc()
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| H A D | xgehal-ring.c | 105 xge_os_dma_sync(ring->channel.pdev, in __hal_ring_rxdblock_link()
209 __hal_ring_initial_replenish(xge_hal_channel_t *channel, in __hal_ring_initial_replenish() argument
214 while (xge_hal_channel_dtr_count(channel) > 0) { in __hal_ring_initial_replenish()
217 status = xge_hal_ring_dtr_reserve(channel, &dtr); in __hal_ring_initial_replenish()
220 if (channel->dtr_init) { in __hal_ring_initial_replenish()
221 status = channel->dtr_init(channel, in __hal_ring_initial_replenish()
222 dtr, channel->reserve_length, in __hal_ring_initial_replenish()
223 channel->userdata, in __hal_ring_initial_replenish()
226 xge_hal_ring_dtr_free(channel, dtr); in __hal_ring_initial_replenish()
227 xge_hal_channel_abort(channel, in __hal_ring_initial_replenish()
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| H A D | xgehal-fifo.c | 88 if (fifo->channel.dtr_init) { in __hal_fifo_mempool_item_alloc()
89 fifo->channel.dtr_init(fifo, (xge_hal_dtr_h)txdp, index, in __hal_fifo_mempool_item_alloc()
90 fifo->channel.userdata, XGE_HAL_CHANNEL_OC_NORMAL); in __hal_fifo_mempool_item_alloc()
125 xge_os_dma_unmap(fifo->channel.pdev, in __hal_fifo_mempool_item_free()
135 xge_os_dma_free(fifo->channel.pdev, in __hal_fifo_mempool_item_free()
159 hldev = (xge_hal_device_t *)fifo->channel.devh; in __hal_fifo_open()
164 xge_os_spin_lock_init(&fifo->channel.reserve_lock, hldev->pdev); in __hal_fifo_open()
166 xge_os_spin_lock_init_irq(&fifo->channel.reserve_lock, hldev->irqh); in __hal_fifo_open()
172 xge_os_spin_lock_init(&fifo->channel.post_lock, hldev->pdev); in __hal_fifo_open()
173 fifo->post_lock_ptr = &fifo->channel.post_lock; in __hal_fifo_open()
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| /titanic_44/usr/src/uts/i86pc/io/ioat/ |
| H A D | ioat_chan.c | 88 static int ioat_completion_alloc(ioat_channel_t channel);
89 static void ioat_completion_free(ioat_channel_t channel);
90 static void ioat_channel_start(ioat_channel_t channel);
91 static void ioat_channel_reset(ioat_channel_t channel);
93 int ioat_ring_alloc(ioat_channel_t channel, uint_t desc_cnt);
94 void ioat_ring_free(ioat_channel_t channel);
95 void ioat_ring_seed(ioat_channel_t channel, ioat_chan_dma_desc_t *desc);
96 int ioat_ring_reserve(ioat_channel_t channel, ioat_channel_ring_t *ring,
155 struct ioat_channel_s *channel; in ioat_channel_alloc() local
174 channel = &state->is_channel[chan_num]; in ioat_channel_alloc()
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| /titanic_44/usr/src/uts/common/io/ |
| H A D | dcopy.c | 158 static int dcopy_stats_init(dcopy_handle_t channel);
159 static void dcopy_stats_fini(dcopy_handle_t channel);
285 dcopy_handle_t channel; in dcopy_alloc() local
301 channel = list_head(&list->dl_list); in dcopy_alloc()
302 if (channel == NULL) { in dcopy_alloc()
312 channel->ch_ref_cnt++; in dcopy_alloc()
313 list_remove(&list->dl_list, channel); in dcopy_alloc()
314 list_insert_tail(&list->dl_list, channel); in dcopy_alloc()
317 *handle = (dcopy_handle_t)channel; in dcopy_alloc()
326 dcopy_free(dcopy_handle_t *channel) in dcopy_free() argument
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| /titanic_44/usr/src/uts/common/io/nxge/npi/ |
| H A D | npi_txdma.c | 36 uint8_t channel);
38 uint8_t channel);
40 uint8_t channel);
297 npi_txdma_log_page_set(npi_handle_t handle, uint8_t channel, in npi_txdma_log_page_set() argument
305 DMA_LOG_PAGE_FN_VALIDATE(channel, cfgp->page_num, cfgp->func_num, in npi_txdma_log_page_set()
314 TX_LOG_REG_WRITE64(handle, TX_LOG_PAGE_VLD_REG, channel, 0); in npi_txdma_log_page_set()
315 TX_LOG_REG_READ64(handle, TX_LOG_PAGE_VLD_REG, channel, &val); in npi_txdma_log_page_set()
322 TX_LOG_REG_READ64(handle, TX_LOG_PAGE_VLD_REG, channel, &val); in npi_txdma_log_page_set()
332 channel, (cfgp->mask & DMA_LOG_PAGE_MASK_MASK)); in npi_txdma_log_page_set()
334 channel, (cfgp->value & DMA_LOG_PAGE_VALUE_MASK)); in npi_txdma_log_page_set()
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| H A D | npi_rxdma.c | 1766 npi_rxdma_rdc_rcr_pktread_update(npi_handle_t handle, uint8_t channel, in npi_rxdma_rdc_rcr_pktread_update() argument
1773 ASSERT(RXDMA_CHANNEL_VALID(channel)); in npi_rxdma_rdc_rcr_pktread_update()
1774 if (!RXDMA_CHANNEL_VALID(channel)) { in npi_rxdma_rdc_rcr_pktread_update()
1777 " channel %d", channel)); in npi_rxdma_rdc_rcr_pktread_update()
1778 return (NPI_FAILURE | NPI_RXDMA_CHANNEL_INVALID(channel)); in npi_rxdma_rdc_rcr_pktread_update()
1788 RXDMA_REG_READ64(handle, RX_DMA_CTL_STAT_REG, channel, in npi_rxdma_rdc_rcr_pktread_update()
1792 channel, cs.value); in npi_rxdma_rdc_rcr_pktread_update()
1798 npi_rxdma_rdc_rcr_bufread_update(npi_handle_t handle, uint8_t channel, in npi_rxdma_rdc_rcr_bufread_update() argument
1805 ASSERT(RXDMA_CHANNEL_VALID(channel)); in npi_rxdma_rdc_rcr_bufread_update()
1806 if (!RXDMA_CHANNEL_VALID(channel)) { in npi_rxdma_rdc_rcr_bufread_update()
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| H A D | npi_txc.c | 267 npi_txc_dma_max_burst(npi_handle_t handle, io_op_t op_mode, uint8_t channel, in npi_txc_dma_max_burst() argument
272 ASSERT(TXDMA_CHANNEL_VALID(channel)); in npi_txc_dma_max_burst()
273 if (!TXDMA_CHANNEL_VALID(channel)) { in npi_txc_dma_max_burst()
277 channel)); in npi_txc_dma_max_burst()
278 return (NPI_FAILURE | NPI_TXC_CHANNEL_INVALID(channel)); in npi_txc_dma_max_burst()
283 TXC_FZC_REG_READ64(handle, TXC_DMA_MAX_BURST_REG, channel, in npi_txc_dma_max_burst()
290 TXC_DMA_MAX_BURST_REG, channel, *dma_max_burst_p); in npi_txc_dma_max_burst()
298 return (NPI_FAILURE | NPI_TXC_OPCODE_INVALID(channel)); in npi_txc_dma_max_burst()
319 npi_txc_dma_max_burst_set(npi_handle_t handle, uint8_t channel, in npi_txc_dma_max_burst_set() argument
322 ASSERT(TXDMA_CHANNEL_VALID(channel)); in npi_txc_dma_max_burst_set()
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| /titanic_44/usr/src/uts/common/io/hxge/ |
| H A D | hpi_txdma.c | 35 uint8_t channel);
38 hpi_txdma_log_page_handle_set(hpi_handle_t handle, uint8_t channel, in hpi_txdma_log_page_handle_set() argument
43 if (!TXDMA_CHANNEL_VALID(channel)) { in hpi_txdma_log_page_handle_set()
46 " Invalid Input: channel <0x%x>", channel)); in hpi_txdma_log_page_handle_set()
47 return (HPI_FAILURE | HPI_TXDMA_CHANNEL_INVALID(channel)); in hpi_txdma_log_page_handle_set()
50 TXDMA_REG_WRITE64(handle, TDC_PAGE_HANDLE, channel, hdl_p->value); in hpi_txdma_log_page_handle_set()
56 hpi_txdma_channel_reset(hpi_handle_t handle, uint8_t channel) in hpi_txdma_channel_reset() argument
59 " hpi_txdma_channel_reset" " RESETTING", channel)); in hpi_txdma_channel_reset()
60 return (hpi_txdma_channel_control(handle, TXDMA_RESET, channel)); in hpi_txdma_channel_reset()
64 hpi_txdma_channel_init_enable(hpi_handle_t handle, uint8_t channel) in hpi_txdma_channel_init_enable() argument
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| H A D | hxge_txdma.c | 59 static hxge_status_t hxge_map_txdma_channel(p_hxge_t hxgep, uint16_t channel,
63 static void hxge_unmap_txdma_channel(p_hxge_t hxgep, uint16_t channel,
73 static hxge_status_t hxge_txdma_start_channel(p_hxge_t hxgep, uint16_t channel,
75 static hxge_status_t hxge_txdma_stop_channel(p_hxge_t hxgep, uint16_t channel,
77 static p_tx_ring_t hxge_txdma_get_ring(p_hxge_t hxgep, uint16_t channel);
80 static p_tx_mbox_t hxge_txdma_get_mbox(p_hxge_t hxgep, uint16_t channel);
82 uint16_t channel, p_tx_ring_t tx_ring_p);
152 hxge_reset_txdma_channel(p_hxge_t hxgep, uint16_t channel, uint64_t reg_data) in hxge_reset_txdma_channel() argument
162 rs = hpi_txdma_channel_reset(handle, channel); in hxge_reset_txdma_channel()
164 rs = hpi_txdma_channel_control(handle, TXDMA_RESET, channel); in hxge_reset_txdma_channel()
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| H A D | hpi_txdma.h | 48 #define HXGE_TXDMA_OFFSET(x, v, channel) (x + \ argument
49 (!v ? DMC_OFFSET(channel) : TDMC_PIOVADDR_OFFSET(channel)))
53 #define TXDMA_REG_READ64(handle, reg, channel, val_p) \ argument
55 (HXGE_TXDMA_OFFSET(reg, handle.is_vraddr, channel)), val_p)
57 #define TXDMA_REG_WRITE64(handle, reg, channel, data) \ argument
59 HXGE_TXDMA_OFFSET(reg, handle.is_vraddr, channel), data)
104 uint8_t channel, tdc_page_handle_t *hdl_p);
105 hpi_status_t hpi_txdma_channel_reset(hpi_handle_t handle, uint8_t channel);
107 uint8_t channel);
108 hpi_status_t hpi_txdma_channel_enable(hpi_handle_t handle, uint8_t channel);
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| H A D | hxge_rxdma.c | 65 static hxge_status_t hxge_map_rxdma_channel(p_hxge_t hxgep, uint16_t channel,
70 static void hxge_unmap_rxdma_channel(p_hxge_t hxgep, uint16_t channel,
79 uint16_t channel, p_hxge_dma_common_t *dma_buf_p,
83 static hxge_status_t hxge_rxdma_start_channel(p_hxge_t hxgep, uint16_t channel,
86 static hxge_status_t hxge_rxdma_stop_channel(p_hxge_t hxgep, uint16_t channel);
95 uint16_t channel);
103 uint16_t channel);
160 hxge_init_rxdma_channel_cntl_stat(p_hxge_t hxgep, uint16_t channel, in hxge_init_rxdma_channel_cntl_stat() argument
171 rs = hpi_rxdma_control_status(handle, OP_SET, channel, cs_p); in hxge_init_rxdma_channel_cntl_stat()
181 hxge_enable_rxdma_channel(p_hxge_t hxgep, uint16_t channel, in hxge_enable_rxdma_channel() argument
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| H A D | hxge_defs.h | 84 #define TDMC_PIOVADDR_OFFSET(channel) (2 * DMA_CSR_SIZE * channel) argument
85 #define RDMC_PIOVADDR_OFFSET(channel) (TDMC_OFFSET(channel) + DMA_CSR_SIZE) argument
90 #define DMC_OFFSET(channel) (DMA_CSR_SIZE * channel) argument
91 #define TDMC_OFFSET(channel) (TX_RNG_CFIG + DMA_CSR_SIZE * channel) argument
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| H A D | hpi_rxdma.h | 106 #define HXGE_RXDMA_OFFSET(x, v, channel) (x + \ argument
107 (!v ? DMC_OFFSET(channel) : \
108 RDMC_PIOVADDR_OFFSET(channel)))
110 #define RXDMA_REG_READ64(handle, reg, channel, data_p) {\ argument
112 channel)), (data_p))\
115 #define RXDMA_REG_READ32(handle, reg, channel, data_p) \ argument
117 channel)), (data_p))
119 #define RXDMA_REG_WRITE64(handle, reg, channel, data) {\ argument
121 channel)), (data))\
190 uint8_t channel, rdc_stat_t *cs_p);
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| /titanic_44/usr/src/uts/common/io/nxge/ |
| H A D | nxge_txdma.c | 91 p_tx_ring_t ring_p, uint16_t channel);
150 int channel) in nxge_init_txdma_channel() argument
156 status = nxge_map_txdma(nxge, channel); in nxge_init_txdma_channel()
160 (void) npi_txdma_dump_tdc_regs(nxge->npi_handle, channel); in nxge_init_txdma_channel()
164 status = nxge_txdma_hw_start(nxge, channel); in nxge_init_txdma_channel()
166 (void) nxge_unmap_txdma_channel(nxge, channel); in nxge_init_txdma_channel()
167 (void) npi_txdma_dump_tdc_regs(nxge->npi_handle, channel); in nxge_init_txdma_channel()
171 if (!nxge->statsp->tdc_ksp[channel]) in nxge_init_txdma_channel()
172 nxge_setup_tdc_kstats(nxge, channel); in nxge_init_txdma_channel()
203 nxge_uninit_txdma_channel(p_nxge_t nxgep, int channel) in nxge_uninit_txdma_channel() argument
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| H A D | nxge_rxdma.c | 140 int i, count, channel; in nxge_init_rxdma_channels() local
166 for (channel = 0; channel < NXGE_MAX_RDCS; channel++) { in nxge_init_rxdma_channels()
167 if ((1 << channel) & map) { in nxge_init_rxdma_channels()
169 group, VP_BOUND_RX, channel))) in nxge_init_rxdma_channels()
188 for (channel = 0; channel < NXGE_MAX_RDCS; channel++) { in nxge_init_rxdma_channels()
189 if ((1 << channel) & map) { in nxge_init_rxdma_channels()
191 VP_BOUND_RX, channel); in nxge_init_rxdma_channels()
204 nxge_init_rxdma_channel(p_nxge_t nxge, int channel) in nxge_init_rxdma_channel() argument
210 status = nxge_map_rxdma(nxge, channel); in nxge_init_rxdma_channel()
220 p_rx_rcr_ring_t ring = nxge->rx_rcr_rings->rcr_rings[channel]; in nxge_init_rxdma_channel()
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| H A D | nxge_hio.c | 401 nxge_grp_dc_remove(nxge, type, group->dc->channel); in nxge_grp_remove()
426 int channel) /* A physical/logical channel number */ in nxge_grp_dc_add() argument
442 if (channel > NXGE_MAX_TDCS) { in nxge_grp_dc_add()
444 "nxge_grp_dc_add: TDC = %d", channel)); in nxge_grp_dc_add()
450 if (channel > NXGE_MAX_RDCS) { in nxge_grp_dc_add()
452 "nxge_grp_dc_add: RDC = %d", channel)); in nxge_grp_dc_add()
459 "nxge_grp_dc_add: unknown type channel(%d)", channel)); in nxge_grp_dc_add()
465 nxge->mac.portnum, group->sequence, group->count, channel)); in nxge_grp_dc_add()
475 if (!(dc = nxge_grp_dc_find(nxge, type, channel))) { in nxge_grp_dc_add()
477 "nxge_grp_dc_add(%d): DC FIND failed", channel)); in nxge_grp_dc_add()
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| H A D | nxge_intr.c | 73 int channel) in nxge_intr_add() argument
87 if ((vector = nxge_intr_vec_find(nxge, type, channel)) == -1) { in nxge_intr_add()
89 "nxge_intr_add(%cDC %d): vector not found", c, channel)); in nxge_intr_add()
111 c, channel, vector, nxge_ddi_perror(status2))); in nxge_intr_add()
122 c, channel, vector, nxge_ddi_perror(status2))); in nxge_intr_add()
163 int channel) in nxge_intr_remove() argument
176 if ((vector = nxge_intr_vec_find(nxge, type, channel)) == -1) { in nxge_intr_remove()
178 "nxge_intr_remove(%cDC %d): vector not found", c, channel)); in nxge_intr_remove()
203 c, channel, vector, nxge_ddi_perror(status2))); in nxge_intr_remove()
212 c, channel, vector, nxge_ddi_perror(status2))); in nxge_intr_remove()
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| H A D | nxge_fzc.c | 282 nxge_init_fzc_rdc(p_nxge_t nxgep, uint16_t channel) in nxge_init_fzc_rdc() argument
300 status = npi_rxdma_cfg_rdc_reset(handle, channel); in nxge_init_fzc_rdc()
304 "returned 0x%08x", channel, status)); in nxge_init_fzc_rdc()
334 status = nxge_init_fzc_rdc_pages(nxgep, channel, in nxge_init_fzc_rdc()
342 status = nxge_init_fzc_rdc_pages(nxgep, channel, in nxge_init_fzc_rdc()
367 status |= npi_rxdma_cfg_wred_param(handle, channel, &red); in nxge_init_fzc_rdc()
393 nxge_init_fzc_rxdma_channel(p_nxge_t nxgep, uint16_t channel) in nxge_init_fzc_rxdma_channel() argument
402 rbr_ring = nxgep->rx_rbr_rings->rbr_rings[channel]; in nxge_init_fzc_rxdma_channel()
403 rcr_ring = nxgep->rx_rcr_rings->rcr_rings[channel]; in nxge_init_fzc_rxdma_channel()
412 status = nxge_init_hv_fzc_rxdma_channel_pages(nxgep, channel, in nxge_init_fzc_rxdma_channel()
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| H A D | nxge_hio_guest.c | 309 dc->channel = (nxge_channel_t)i; in nxge_hio_vr_add()
342 dc->channel = (nxge_channel_t)i; in nxge_hio_vr_add()
414 nxge_hio_get_dc_htable_idx(nxge_t *nxge, vpc_type_t type, uint32_t channel) in nxge_hio_get_dc_htable_idx() argument
420 dc = nxge_grp_dc_find(nxge, type, channel); in nxge_hio_get_dc_htable_idx()
602 int channel) in nxge_tdc_lp_conf() argument
614 ring = nxge->tx_rings->rings[channel]; in nxge_tdc_lp_conf()
621 if (!(dc = nxge_grp_dc_find(nxge, VP_BOUND_TX, channel))) in nxge_tdc_lp_conf()
630 data = nxge->tx_buf_pool_p->dma_buf_pool_p[channel]; in nxge_tdc_lp_conf()
635 (uint64_t)channel, 0, in nxge_tdc_lp_conf()
644 channel, hv_rv, in nxge_tdc_lp_conf()
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| /titanic_44/usr/src/uts/intel/io/intel_nhm/ |
| H A D | mem_addr.c | 52 channel_in_interleave(int node, int channel, int rule, int *way_p, in channel_in_interleave() argument
65 if (channel > 1) in channel_in_interleave()
72 c = 1 << channel; in channel_in_interleave()
158 channel_address(int node, int channel, int rule, uint64_t addr) in channel_address() argument
163 channel = 0; in channel_address()
165 (int64_t)sag_ch[node][channel][rule].soffset) << 16) | in channel_address()
167 if (sag_ch[node][channel][rule].remove8) { in channel_address()
170 if (sag_ch[node][channel][rule].remove7) { in channel_address()
173 if (sag_ch[node][channel][rule].remove6) { in channel_address()
177 if (sag_ch[node][channel][rule].divby3) { in channel_address()
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| H A D | intel_nhm.h | 76 #define MC_CHANNEL_RANK_PRESENT_RD(cpu, channel) \ argument
77 nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 0, 0x7c, 0)
78 #define MC_DOD_RD(cpu, channel, select) \ argument
79 nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 1, 0x48 + ((select) * 4), 0)
80 #define MC_SAG_RD(cpu, channel, select) \ argument
81 nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 1, 0x80 + ((select) * 4), 0)
82 #define MC_RIR_LIMIT_RD(cpu, channel, select) \ argument
83 nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 2, 0x40 + ((select) * 4), 0)
84 #define MC_RIR_WAY_RD(cpu, channel, select) \ argument
85 nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 2, 0x80 + ((select) * 4), 0)
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| /titanic_44/usr/src/uts/sun4u/io/i2c/clients/ |
| H A D | tda8444.c | 164 int channel; in tda8444_do_resume() local
175 for (channel = 0; channel < TDA8444_CHANS; channel++) { in tda8444_do_resume()
177 channel; in tda8444_do_resume()
179 unitp->tda8444_output[channel]; in tda8444_do_resume()
181 channel, unitp->tda8444_output[channel])); in tda8444_do_resume()
353 int channel = TDA8444_MINOR_TO_CHANNEL(*devp); in tda8444_open() local
376 if (unitp->tda8444_oflag[channel] != 0) { in tda8444_open()
379 unitp->tda8444_oflag[channel] = FEXCL; in tda8444_open()
382 if (unitp->tda8444_oflag[channel] == FEXCL) { in tda8444_open()
385 unitp->tda8444_oflag[channel] = (uint16_t)FOPEN; in tda8444_open()
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| /titanic_44/usr/src/lib/libipmi/common/ |
| H A D | ipmi_lancfg.c | 98 ipmi_lan_get_param(ipmi_handle_t *ihp, int channel, int param, int set, in ipmi_lan_get_param() argument
104 lcmd.ilgc_number = channel; in ipmi_lan_get_param()
133 ipmi_lan_get_config(ipmi_handle_t *ihp, int channel, ipmi_lan_config_t *cfgp) in ipmi_lan_get_config() argument
139 if (ipmi_lan_get_param(ihp, channel, IPMI_LAN_PARAM_SET_IN_PROGRESS, 0, in ipmi_lan_get_config()
150 if (ipmi_lan_get_param(ihp, channel, lep->ile_param, in ipmi_lan_get_config()
160 ipmi_lan_set_param(ipmi_handle_t *ihp, int channel, int param, void *data, in ipmi_lan_set_param() argument
166 lcmd.ilsc_number = channel; in ipmi_lan_set_param()
201 ipmi_lan_set_config(ipmi_handle_t *ihp, int channel, ipmi_lan_config_t *cfgp, in ipmi_lan_set_config() argument
212 if (ipmi_lan_set_param(ihp, channel, IPMI_LAN_PARAM_SET_IN_PROGRESS, in ipmi_lan_set_config()
216 if (ipmi_lan_set_param(ihp, channel, IPMI_LAN_PARAM_SET_IN_PROGRESS, in ipmi_lan_set_config()
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