1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at 9 * http://www.opensource.org/licenses/cddl1.txt. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2004-2011 Emulex. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _EMLXS_OS_H 28 #define _EMLXS_OS_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 #define EMLXS_MODREV2 2 /* Old Solaris 8 & 9 interface */ 35 #define EMLXS_MODREV3 3 /* New Solaris 10 & 11 interface */ 36 #define EMLXS_MODREV4 4 /* Sun FC packet change */ 37 /* Symbolic Node Name interface */ 38 #define EMLXS_MODREV5 5 /* New Sun NPIV Interface */ 39 40 #define EMLXS_MODREV2X 2 /* Old Solaris 8 & 9 x86 interface */ 41 #define EMLXS_MODREV3X 3 /* New Solaris 10 & 11 x86 interface */ 42 43 44 /* 45 * DRIVER LEVEL FEATURES 46 */ 47 #define DHCHAP_SUPPORT /* 2.21 driver */ 48 49 #define SATURN_MSI_SUPPORT /* 2.30 driver */ 50 #define MENLO_SUPPORT /* 2.30 driver */ 51 #define MBOX_EXT_SUPPORT /* 2.30 driver */ 52 53 #define DUMP_SUPPORT /* 2.40 driver */ 54 #define SAN_DIAG_SUPPORT /* 2.40 driver */ 55 #define FMA_SUPPORT /* 2.40 driver */ 56 57 #define NODE_THROTTLE_SUPPORT /* 2.70 driver */ 58 59 /* #define IDLE_TIMER Not yet - untested */ 60 61 /* 62 * OS LEVEL FEATURES 63 */ 64 65 66 #ifdef S11 67 #define MSI_SUPPORT 68 #define SFCT_SUPPORT /* COMSTAR Support */ 69 #define MODFW_SUPPORT /* Dynamic firmware module support */ 70 #define EMLXS_MODREV EMLXS_MODREV5 /* Sun NPIV Enhancement */ 71 72 #ifdef EMLXS_I386 73 #define EMLXS_MODREVX EMLXS_MODREV2X 74 #endif /* i386 */ 75 #endif /* S11 */ 76 77 /* 78 * SUBFEATURES 79 */ 80 #ifdef SFCT_SUPPORT 81 #define MODSYM_SUPPORT /* Dynamic Module Loading Support */ 82 #define FCIO_SUPPORT /* FCIO IOCTL support */ 83 #endif /* SFCT_SUPPORT */ 84 85 86 #ifndef EMLXS_MODREV 87 #define EMLXS_MODREV 0 88 #endif /* EMLXS_MODREV */ 89 90 #ifndef EMLXS_MODREVX 91 #define EMLXS_MODREVX 0 92 #endif /* EMLXS_MODREVX */ 93 94 /* Create combined definition */ 95 #if defined(S10) || defined(S11) 96 #define S10S11 97 #endif /* S10 or S11 */ 98 99 #include <sys/types.h> 100 #include <sys/varargs.h> 101 #include <sys/devops.h> 102 #include <sys/param.h> 103 #include <sys/user.h> 104 #include <sys/buf.h> 105 #include <sys/ioctl.h> 106 #include <sys/uio.h> 107 #include <sys/fcntl.h> 108 109 #include <sys/cmn_err.h> 110 #include <sys/stropts.h> 111 #include <sys/kmem.h> 112 113 #include <sys/errno.h> 114 #include <sys/open.h> 115 #include <sys/kmem.h> 116 #include <sys/poll.h> 117 #include <sys/thread.h> 118 #include <sys/taskq.h> 119 #include <sys/debug.h> 120 #include <sys/cpu.h> 121 #include <sys/autoconf.h> 122 #include <sys/conf.h> 123 #include <sys/stat.h> 124 #include <sys/var.h> 125 126 #include <sys/map.h> 127 #include <sys/file.h> 128 #include <sys/syslog.h> 129 #include <sys/disp.h> 130 #include <sys/taskq.h> 131 132 #include <sys/ddi.h> 133 #include <sys/sunddi.h> 134 #include <sys/promif.h> 135 #include <sys/ethernet.h> 136 #include <vm/seg_kmem.h> 137 #include <sys/utsname.h> 138 #include <sys/modctl.h> 139 #include <sys/scsi/scsi.h> 140 #include <sys/varargs.h> 141 #include <sys/atomic.h> 142 #ifdef S11 143 #include <sys/pci.h> 144 #include <sys/pcie.h> 145 #else /* !S11 */ 146 /* 147 * Capabilities linked list entry offsets 148 */ 149 #define PCI_CAP_ID 0x0 /* capability identifier, 1 byte */ 150 #define PCI_CAP_NEXT_PTR 0x1 /* next entry pointer, 1 byte */ 151 #define PCI_CAP_ID_REGS_OFF 0x2 /* cap id register offset */ 152 #define PCI_CAP_MAX_PTR 0x30 /* maximum number of cap pointers */ 153 #define PCI_CAP_PTR_OFF 0x40 /* minimum cap pointer offset */ 154 #define PCI_CAP_PTR_MASK 0xFC /* mask for capability pointer */ 155 156 /* 157 * Capability identifier values 158 */ 159 #define PCI_CAP_ID_PM 0x1 /* power management entry */ 160 #define PCI_CAP_ID_AGP 0x2 /* AGP supported */ 161 #define PCI_CAP_ID_VPD 0x3 /* VPD supported */ 162 #define PCI_CAP_ID_SLOT_ID 0x4 /* Slot Identification supported */ 163 #define PCI_CAP_ID_MSI 0x5 /* MSI supported */ 164 #define PCI_CAP_ID_cPCI_HS 0x6 /* CompactPCI Host Swap supported */ 165 #define PCI_CAP_ID_PCIX 0x7 /* PCI-X supported */ 166 #define PCI_CAP_ID_HT 0x8 /* HyperTransport supported */ 167 #define PCI_CAP_ID_VS 0x9 /* Vendor Specific */ 168 #define PCI_CAP_ID_DEBUG_PORT 0xA /* Debug Port supported */ 169 #define PCI_CAP_ID_cPCI_CRC 0xB /* CompactPCI central resource ctrl */ 170 #define PCI_CAP_ID_PCI_HOTPLUG 0xC /* PCI Hot Plug supported */ 171 #define PCI_CAP_ID_P2P_SUBSYS 0xD /* PCI bridge Sub-system ID */ 172 #define PCI_CAP_ID_AGP_8X 0xE /* AGP 8X supported */ 173 #define PCI_CAP_ID_SECURE_DEV 0xF /* Secure Device supported */ 174 #define PCI_CAP_ID_PCI_E 0x10 /* PCI Express supported */ 175 #define PCI_CAP_ID_MSI_X 0x11 /* MSI-X supported */ 176 #define PCI_CAP_ID_SATA 0x12 /* SATA Data/Index Config supported */ 177 #define PCI_CAP_ID_FLR 0x13 /* Function Level Reset supported */ 178 179 /* 180 * PCI power management (PM) capability entry offsets 181 */ 182 #define PCI_PMCAP 0x2 /* PM capabilities, 2 bytes */ 183 #define PCI_PMCSR 0x4 /* PM control/status reg, 2 bytes */ 184 #define PCI_PMCSR_BSE 0x6 /* PCI-PCI bridge extensions, 1 byte */ 185 #define PCI_PMDATA 0x7 /* PM data, 1 byte */ 186 187 /* 188 * PM control/status values - 2 bytes 189 */ 190 #define PCI_PMCSR_D0 0x0 /* power state D0 */ 191 #define PCI_PMCSR_D1 0x1 /* power state D1 */ 192 #define PCI_PMCSR_D2 0x2 /* power state D2 */ 193 #define PCI_PMCSR_D3HOT 0x3 /* power state D3hot */ 194 195 196 /* 197 * PCI Express capability registers in PCI configuration space relative to 198 * the PCI Express Capability structure. 199 */ 200 #define PCIE_CAP_ID PCI_CAP_ID 201 #define PCIE_CAP_NEXT_PTR PCI_CAP_NEXT_PTR 202 #define PCIE_PCIECAP 0x02 /* PCI-e Capability Reg */ 203 #define PCIE_DEVCAP 0x04 /* Device Capability */ 204 #define PCIE_DEVCTL 0x08 /* Device Control */ 205 #define PCIE_DEVSTS 0x0A /* Device Status */ 206 #define PCIE_LINKCAP 0x0C /* Link Capability */ 207 #define PCIE_LINKCTL 0x10 /* Link Control */ 208 #define PCIE_LINKSTS 0x12 /* Link Status */ 209 #define PCIE_SLOTCAP 0x14 /* Slot Capability */ 210 #define PCIE_SLOTCTL 0x18 /* Slot Control */ 211 #define PCIE_SLOTSTS 0x1A /* Slot Status */ 212 #define PCIE_ROOTCTL 0x1C /* Root Control */ 213 #define PCIE_ROOTSTS 0x20 /* Root Status */ 214 215 /* 216 * PCI-Express Enhanced Capabilities Link Entry Bit Offsets 217 */ 218 #define PCIE_EXT_CAP 0x100 /* Base Address of Ext Cap */ 219 220 #define PCIE_EXT_CAP_ID_SHIFT 0 /* PCI-e Ext Cap ID */ 221 #define PCIE_EXT_CAP_ID_MASK 0xFFFF 222 #define PCIE_EXT_CAP_VER_SHIFT 16 /* PCI-e Ext Cap Ver */ 223 #define PCIE_EXT_CAP_VER_MASK 0xF 224 #define PCIE_EXT_CAP_NEXT_PTR_SHIFT 20 /* PCI-e Ext Cap Next Ptr */ 225 #define PCIE_EXT_CAP_NEXT_PTR_MASK 0xFFF 226 227 #define PCIE_EXT_CAP_NEXT_PTR_NULL 0x0 228 229 /* 230 * PCI-Express Enhanced Capability Identifier Values 231 */ 232 #define PCIE_EXT_CAP_ID_AER 0x1 /* Advanced Error Handling */ 233 #define PCIE_EXT_CAP_ID_VC 0x2 /* Virtual Channel, no MFVC */ 234 #define PCIE_EXT_CAP_ID_SER 0x3 /* Serial Number */ 235 #define PCIE_EXT_CAP_ID_PWR_BUDGET 0x4 /* Power Budgeting */ 236 #define PCIE_EXT_CAP_ID_RC_LINK_DECL 0x5 /* RC Link Declaration */ 237 #define PCIE_EXT_CAP_ID_RC_INT_LINKCTRL 0x6 /* RC Internal Link Control */ 238 #define PCIE_EXT_CAP_ID_RC_EVNT_CEA 0x7 /* RC Event Collector */ 239 /* Endpoint Association */ 240 #define PCIE_EXT_CAP_ID_MFVC 0x8 /* Multi-func Virtual Channel */ 241 #define PCIE_EXT_CAP_ID_VC_WITH_MFVC 0x9 /* Virtual Channel w/ MFVC */ 242 #define PCIE_EXT_CAP_ID_RCRB 0xA /* Root Complex Register Blck */ 243 #define PCIE_EXT_CAP_ID_VS 0xB /* Vendor Spec Extended Cap */ 244 #define PCIE_EXT_CAP_ID_CAC 0xC /* Config Access Correlation */ 245 #define PCIE_EXT_CAP_ID_ACS 0xD /* Access Control Services */ 246 #define PCIE_EXT_CAP_ID_ARI 0xE /* Alternative Routing ID */ 247 #define PCIE_EXT_CAP_ID_ATS 0xF /* Address Translation Svcs */ 248 #endif /* S11 */ 249 250 #include <emlxs_hbaapi.h> 251 252 #ifdef FMA_SUPPORT 253 #include <sys/ddifm.h> 254 #include <sys/fm/protocol.h> 255 #include <sys/fm/util.h> 256 #endif /* FMA_SUPPORT */ 257 #include <sys/fm/io/ddi.h> 258 259 #ifdef S11 260 261 /* ULP header files */ 262 #include <sys/fibre-channel/fc.h> 263 #include <sys/fibre-channel/impl/fc_fcaif.h> 264 265 #else /* !S11 */ 266 267 /* ULP header files */ 268 #include <sys/fibre-channel/fcio.h> 269 #include <sys/fibre-channel/fc.h> 270 #include <sys/fibre-channel/fc_appif.h> 271 #include <sys/fibre-channel/fc_types.h> 272 #include <sys/fibre-channel/impl/fc_error.h> 273 #include <sys/fibre-channel/impl/fc_fla.h> 274 #include <sys/fibre-channel/impl/fc_linkapp.h> 275 #include <sys/fibre-channel/impl/fcal.h> 276 #include <sys/fibre-channel/impl/fcgs2.h> 277 #include <sys/fibre-channel/impl/fcph.h> 278 #include <sys/fibre-channel/impl/fc_ulpif.h> 279 #include <sys/fibre-channel/impl/fc_fcaif.h> 280 #include <sys/fibre-channel/impl/fctl.h> 281 #include <sys/fibre-channel/impl/fctl_private.h> 282 #include <sys/fibre-channel/ulp/fcp.h> 283 #include <sys/fibre-channel/ulp/fcp_util.h> 284 285 #endif /* S11 */ 286 287 #ifndef FC_HBA_PORTSPEED_8GBIT 288 #define FC_HBA_PORTSPEED_8GBIT 16 289 #endif /* FC_HBA_PORTSPEED_8GBIT */ 290 291 #ifndef FP_DEFAULT_SID 292 #define FP_DEFAULT_SID (0x000AE) 293 #endif /* FP_DEFAULT_SID */ 294 295 #ifndef FP_DEFAULT_DID 296 #define FP_DEFAULT_DID (0x000EA) 297 #endif /* FP_DEFAULT_DID */ 298 299 #ifdef MSI_SUPPORT 300 #pragma weak ddi_intr_get_supported_types 301 #pragma weak ddi_intr_get_nintrs 302 #pragma weak ddi_intr_add_handler 303 #pragma weak ddi_intr_remove_handler 304 #pragma weak ddi_intr_get_hilevel_pri 305 #pragma weak ddi_intr_enable 306 #pragma weak ddi_intr_disable 307 #pragma weak ddi_intr_get_cap 308 #pragma weak ddi_intr_get_pri 309 #pragma weak ddi_intr_alloc 310 #pragma weak ddi_intr_free 311 #pragma weak ddi_intr_block_enable 312 #pragma weak ddi_intr_block_disable 313 extern int ddi_intr_get_supported_types(); 314 #endif /* MSI_SUPPORT */ 315 316 #ifndef MODSYM_SUPPORT 317 #pragma weak fc_fca_init 318 #pragma weak fc_fca_attach 319 #pragma weak fc_fca_detach 320 #endif /* MODSYM_SUPPORT */ 321 322 /* S11 flag for dma_attr_flags for ddi_dma_attr_t */ 323 #ifndef DDI_DMA_RELAXED_ORDERING 324 #define DDI_DMA_RELAXED_ORDERING 0x400 325 #endif /* DDI_DMA_RELAXED_ORDERING */ 326 327 #ifdef FMA_SUPPORT 328 /* FMA Support */ 329 #pragma weak ddi_fm_acc_err_clear 330 extern void ddi_fm_acc_err_clear(); 331 #endif /* FMA_SUPPORT */ 332 333 #ifdef EMLXS_SPARC 334 #define EMLXS_BIG_ENDIAN 335 #endif /* EMLXS_SPARC */ 336 337 #ifdef EMLXS_I386 338 #define EMLXS_LITTLE_ENDIAN 339 #endif /* EMLXS_I386 */ 340 341 342 /* Solaris 8 does not define this */ 343 #ifndef TASKQ_DYNAMIC 344 #define TASKQ_DYNAMIC 0x0004 345 #endif /* TASKQ_DYNAMIC */ 346 347 #ifdef _LP64 348 #define DEAD_PTR 0xdeadbeefdeadbeef 349 #else 350 #define DEAD_PTR 0xdeadbeef 351 #endif /* _LP64 */ 352 353 #ifndef FC_STATE_8GBIT_SPEED 354 /* This was obtained from OpenSolaris */ 355 #define FC_STATE_8GBIT_SPEED 0x0700 /* 8 Gbit/sec */ 356 #endif /* FC_STATE_8GBIT_SPEED */ 357 358 #define FC_STATE_QUAD_SPEED 0x0500 359 360 #ifndef BURSTSIZE 361 #define BURSTSIZE 362 #define BURST1 0x01 363 #define BURST2 0x02 364 #define BURST4 0x04 365 #define BURST8 0x08 366 #define BURST16 0x10 367 #define BURST32 0x20 368 #define BURST64 0x40 369 #ifdef _LP64 370 #define BURSTSIZE_MASK 0x7f 371 #else 372 #define BURSTSIZE_MASK 0x3f 373 #endif /* _LP64 */ 374 #define DEFAULT_BURSTSIZE (BURSTSIZE_MASK) /* all burst sizes */ 375 #endif /* BURSTSIZE */ 376 377 #define PADDR_LO(addr) ((uint32_t)(((uint64_t)(addr)) & 0xffffffff)) 378 #define PADDR_HI(addr) ((uint32_t)(((uint64_t)(addr)) >> 32)) 379 #define PADDR(high, low) ((uint64_t)((((uint64_t)(high)) << 32) \ 380 | (((uint64_t)(low)) & 0xffffffff))) 381 382 #ifndef TRUE 383 #define TRUE 1 384 #endif /* TRUE */ 385 386 #ifndef FALSE 387 #define FALSE 0 388 #endif /* FALSE */ 389 390 #define DMA_READ_WRITE 0 391 #define DMA_READ_ONLY 1 392 #define DMA_WRITE_ONLY 2 393 394 #define DMA_SUCC 1 395 396 #define MAX_FC_BRDS 256 /* Maximum # boards per system */ 397 398 #define BUSYWAIT_MS(ms) drv_usecwait((ms*1000)) 399 #define BUSYWAIT_US(us) drv_usecwait(us) 400 401 #define EMLXS_MPDATA_SYNC(h, a, b, c) \ 402 if (h) { \ 403 (void) ddi_dma_sync((ddi_dma_handle_t)(h), \ 404 (off_t)(a), (size_t)(b), (uint_t)c); \ 405 } 406 407 #define PKT2PRIV(pkt) ((emlxs_buf_t *)(pkt)->pkt_fca_private) 408 #define PRIV2PKT(sbp) sbp->pkt 409 410 #define EMLXS_INUMBER 0 411 #define EMLXS_MSI_INUMBER 0 412 413 #define EMLXS_DMA_ALIGN BURST16 414 415 /* 416 * Register indices in PCI configuration space. 417 */ 418 #define SBUS_FLASH_RD 0 /* FCODE-Flash Read only */ 419 /* index */ 420 #define SBUS_FLASH_RDWR 1 /* FCODE-Flash Read/Write */ 421 /* index */ 422 #define SBUS_DFLY_SLIM_RINDEX 2 /* DragonFly SLIM regs index */ 423 #define SBUS_DFLY_CSR_RINDEX 3 /* DragonFly I/O regs index */ 424 #define SBUS_TITAN_CORE_RINDEX 4 /* TITAN Core register index */ 425 #define SBUS_DFLY_PCI_CFG_RINDEX 5 /* DragonFly PCI ConfigSpace */ 426 /* regs index */ 427 #define SBUS_TITAN_PCI_CFG_RINDEX 6 /* TITAN PCI ConfigSpace regs */ 428 /* index */ 429 #define SBUS_TITAN_CSR_RINDEX 7 /* TITAN Control/Status regs */ 430 /* index */ 431 432 #define PCI_CFG_RINDEX 0 433 #define PCI_SLIM_RINDEX 1 434 #define PCI_CSR_RINDEX 2 435 436 #define PCI_BAR0_RINDEX 1 437 #define PCI_BAR1_RINDEX 2 438 #define PCI_BAR2_RINDEX 3 439 440 441 #define EMLXS_MAX_UBUFS 65535 442 443 /* Tokens < EMLXS_UB_TOKEN_OFFSET are reserved for ELS response oxids */ 444 #define EMLXS_UB_TOKEN_OFFSET 0x100 445 446 typedef struct emlxs_ub_priv 447 { 448 fc_unsol_buf_t *ubp; 449 void *port; 450 451 uint32_t bpl_size; 452 uint8_t *bpl_virt; /* virtual address ptr */ 453 uint64_t bpl_phys; /* mapped address */ 454 void *bpl_data_handle; 455 void *bpl_dma_handle; 456 457 uint32_t ip_ub_size; 458 uint8_t *ip_ub_virt; /* virtual address ptr */ 459 ddi_dma_cookie_t ip_ub_dma_cookies[64]; 460 ddi_acc_handle_t ip_ub_data_handle; 461 ddi_dma_handle_t ip_ub_dma_handle; 462 uint32_t ip_ub_cookie_cnt; 463 uint32_t FC4type; 464 465 uint16_t flags; 466 #define EMLXS_UB_FREE 0x0000 467 #define EMLXS_UB_IN_USE 0x0001 468 #define EMLXS_UB_REPLY 0x0002 469 #define EMLXS_UB_RESV 0x0004 470 #define EMLXS_UB_TIMEOUT 0x0008 471 #define EMLXS_UB_INTERCEPT 0x0010 472 473 uint16_t available; 474 475 uint32_t timeout; /* Timeout period in seconds */ 476 uint32_t time; /* EMLXS_UB_IN_USE timestamp */ 477 uint32_t cmd; 478 uint32_t token; 479 480 struct emlxs_unsol_buf *pool; 481 struct emlxs_ub_priv *next; 482 } emlxs_ub_priv_t; 483 484 485 typedef struct emlxs_unsol_buf 486 { 487 struct emlxs_unsol_buf *pool_prev; /* ptr to prev type */ 488 /* of unsol_buf hdr */ 489 struct emlxs_unsol_buf *pool_next; /* ptr to next type */ 490 /* of unsol_buf hdr */ 491 492 uint32_t pool_type; /* FC-4 type */ 493 uint32_t pool_buf_size; /* buffer size for */ 494 /* this pool */ 495 496 uint32_t pool_nentries; /* no. of bufs in */ 497 /* pool */ 498 uint32_t pool_available; /* no. of bufs avail */ 499 /* in pool */ 500 501 uint32_t pool_flags; 502 #define POOL_DESTROY 0x00000001 /* Pool is marked for */ 503 /* destruction */ 504 505 uint32_t pool_free; /* Number of free */ 506 /* buffers */ 507 uint32_t pool_free_resv; /* Number of free */ 508 /* reserved buffers */ 509 510 uint32_t pool_first_token; /* First token */ 511 /* in pool */ 512 uint32_t pool_last_token; /* Last token */ 513 /* in pool */ 514 515 fc_unsol_buf_t *fc_ubufs; /* array of unsol buf */ 516 /* structs */ 517 } emlxs_unsol_buf_t; 518 519 520 #ifndef FC_REASON_NONE 521 #define FC_REASON_NONE 0 522 #endif /* FC_REASON_NONE */ 523 524 #ifndef FC_ACTION_NONE 525 #define FC_ACTION_NONE 0 526 #endif /* FC_ACTION_NONE */ 527 528 /* 529 * emlx status translation table 530 */ 531 typedef struct emlxs_xlat_err 532 { 533 uint32_t emlxs_status; 534 uint32_t pkt_state; 535 uint32_t pkt_reason; 536 uint32_t pkt_expln; 537 uint32_t pkt_action; 538 } emlxs_xlat_err_t; 539 540 541 typedef struct emlxs_table 542 { 543 uint32_t code; 544 char string[48]; 545 } emlxs_table_t; 546 547 548 /* PATCH MASK DEFINES */ 549 #define EMLXS_PATCH1 0x00000001 550 #define EMLXS_PATCH2 0x00000002 551 #define EMLXS_PATCH3 0x00000004 552 #define EMLXS_PATCH4 0x00000008 553 #define EMLXS_PATCH5 0x00000010 554 #define EMLXS_PATCH6 0x00000020 555 #define EMLXS_PATCH7 0x00000040 556 #define EMLXS_PATCH8 0x00000080 557 #define EMLXS_PATCH9 0x00000100 558 #define EMLXS_PATCH10 0x00000200 559 #define EMLXS_PATCH11 0x00000400 560 #define EMLXS_PATCH12 0x00000800 561 #define EMLXS_PATCH13 0x00001000 562 #define EMLXS_PATCH14 0x00002000 563 #define EMLXS_PATCH15 0x00004000 564 #define EMLXS_PATCH16 0x00008000 565 #define EMLXS_PATCH17 0x00010000 566 #define EMLXS_PATCH18 0x00020000 567 #define EMLXS_PATCH19 0x00040000 568 #define EMLXS_PATCH20 0x00080000 569 #define EMLXS_PATCH21 0x00100000 570 #define EMLXS_PATCH22 0x00200000 571 #define EMLXS_PATCH23 0x00400000 572 #define EMLXS_PATCH24 0x00800000 573 #define EMLXS_PATCH25 0x01000000 574 #define EMLXS_PATCH26 0x02000000 575 #define EMLXS_PATCH27 0x04000000 576 #define EMLXS_PATCH28 0x08000000 577 #define EMLXS_PATCH29 0x10000000 578 #define EMLXS_PATCH30 0x20000000 579 #define EMLXS_PATCH31 0x40000000 580 #define EMLXS_PATCH32 0x80000000 581 582 583 /* ULP Patches: */ 584 585 /* This patch enables the driver to auto respond to unsolicited LOGO's */ 586 /* This is needed because ULP is sometimes doesn't reply itself */ 587 #define ULP_PATCH2 EMLXS_PATCH2 588 589 /* This patch enables the driver to auto respond to unsolicited PRLI's */ 590 /* This is needed because ULP is known to panic sometimes */ 591 #define ULP_PATCH3 EMLXS_PATCH3 592 593 /* This patch enables the driver to auto respond to unsolicited PRLO's */ 594 /* This is needed because ULP is known to panic sometimes */ 595 #define ULP_PATCH4 EMLXS_PATCH4 596 597 /* This patch enables the driver to fail pkt abort requests */ 598 #define ULP_PATCH5 EMLXS_PATCH5 599 600 /* This patch enables the driver to generate an RSCN for unsolicited PRLO's */ 601 /* and LOGO's */ 602 #define ULP_PATCH6 EMLXS_PATCH6 603 604 /* Sun Disk Array Patches: */ 605 606 /* This patch enables the driver to fix a residual underrun issue with */ 607 /* check conditions */ 608 #define FCP_UNDERRUN_PATCH1 EMLXS_PATCH9 609 610 /* This patch enables the driver to fix a residual underrun issue with */ 611 /* SCSI inquiry commands */ 612 #define FCP_UNDERRUN_PATCH2 EMLXS_PATCH10 613 614 615 #define DEFAULT_PATCHES (ULP_PATCH2 | ULP_PATCH3 | \ 616 ULP_PATCH5 | ULP_PATCH6 | \ 617 FCP_UNDERRUN_PATCH1 | FCP_UNDERRUN_PATCH2) 618 619 #ifdef __cplusplus 620 } 621 #endif 622 623 #endif /* _EMLXS_OS_H */ 624