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Searched refs:adapter (Results 1 – 25 of 85) sorted by relevance

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/titanic_44/usr/src/uts/common/io/chxge/com/
H A Dch_subr.c63 int t1_wait_op_done(adapter_t *adapter, int reg, u32 mask, int polarity, in t1_wait_op_done() argument
67 u32 val = t1_read_reg_4(adapter, reg) & mask; in t1_wait_op_done()
86 __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value) in __t1_tpi_write() argument
90 t1_write_reg_4(adapter, A_TPI_ADDR, addr); in __t1_tpi_write()
91 t1_write_reg_4(adapter, A_TPI_WR_DATA, value); in __t1_tpi_write()
92 t1_write_reg_4(adapter, A_TPI_CSR, F_TPIWR); in __t1_tpi_write()
94 tpi_busy = t1_wait_op_done(adapter, A_TPI_CSR, F_TPIRDY, 1, in __t1_tpi_write()
98 adapter_name(adapter), addr); in __t1_tpi_write()
103 t1_tpi_write(adapter_t *adapter, u32 addr, u32 value) in t1_tpi_write() argument
107 TPI_LOCK(adapter); in t1_tpi_write()
[all …]
H A Despi.c33 adapter_t *adapter; member
49 static int tricn_write(adapter_t *adapter, int bundle_addr, int module_addr, in tricn_write() argument
54 t1_write_reg_4(adapter, A_ESPI_CMD_ADDR, V_WRITE_DATA(wr_data) | in tricn_write()
59 t1_write_reg_4(adapter, A_ESPI_GOSTAT, 0); in tricn_write()
61 busy = t1_wait_op_done(adapter, A_ESPI_GOSTAT, F_ESPI_CMD_BUSY, 0, in tricn_write()
65 CH_ERR("%s: TRICN write timed out\n", adapter_name(adapter)); in tricn_write()
71 static int tricn_read(adapter_t *adapter, int bundle_addr, int module_addr,
77 t1_write_reg_4(adapter, A_ESPI_CMD_ADDR,
82 t1_write_reg_4(adapter, A_ESPI_GOSTAT, 0);
85 status = t1_read_reg_4(adapter, A_ESPI_GOSTAT);
[all …]
H A Dmc3.c37 adapter_t *adapter; member
48 u32 en = t1_read_reg_4(mc3->adapter, A_PL_ENABLE); in t1_mc3_intr_enable()
50 if (t1_is_asic(mc3->adapter)) { in t1_mc3_intr_enable()
51 t1_write_reg_4(mc3->adapter, A_MC3_INT_ENABLE, MC3_INTR_MASK); in t1_mc3_intr_enable()
52 t1_write_reg_4(mc3->adapter, A_PL_ENABLE, en | F_PL_INTR_MC3); in t1_mc3_intr_enable()
55 t1_write_reg_4(mc3->adapter, FPGA_MC3_REG_INTRENABLE, in t1_mc3_intr_enable()
57 t1_write_reg_4(mc3->adapter, A_PL_ENABLE, in t1_mc3_intr_enable()
65 u32 pl_intr = t1_read_reg_4(mc3->adapter, A_PL_ENABLE); in t1_mc3_intr_disable()
67 if (t1_is_asic(mc3->adapter)) { in t1_mc3_intr_disable()
68 t1_write_reg_4(mc3->adapter, A_MC3_INT_ENABLE, 0); in t1_mc3_intr_disable()
[all …]
H A Dmc4.c35 adapter_t *adapter; member
46 #define is_MC4A(adapter) (!t1_is_T1B(adapter)) argument
49 static unsigned int __devinit mc4_calc_size(adapter_t *adapter) in mc4_calc_size() argument
51 u32 mc4_cfg = t1_read_reg_4(adapter, A_MC4_CFG); in mc4_calc_size()
52 unsigned int width = is_MC4A(adapter) ? G_MC4A_WIDTH(mc4_cfg) : in mc4_calc_size()
64 static int wrreg_wait(adapter_t *adapter, unsigned int addr, u32 val) in wrreg_wait() argument
68 t1_write_reg_4(adapter, addr, val); in wrreg_wait()
69 val = t1_read_reg_4(adapter, addr); /* flush */ in wrreg_wait()
71 if (!(t1_read_reg_4(adapter, addr) & F_BUSY)) in wrreg_wait()
77 adapter_name(adapter), addr); in wrreg_wait()
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H A Dtp.c36 adapter_t *adapter; member
52 static void tp_pm_configure(adapter_t *adapter, struct tp_params *p) in tp_pm_configure() argument
64 t1_write_reg_4(adapter, A_TP_PM_SIZE, p->pm_size); in tp_pm_configure()
65 t1_write_reg_4(adapter, A_TP_PM_RX_BASE, p->pm_rx_base); in tp_pm_configure()
66 t1_write_reg_4(adapter, A_TP_PM_TX_BASE, p->pm_tx_base); in tp_pm_configure()
67 t1_write_reg_4(adapter, A_TP_PM_DEFRAG_BASE, p->pm_size); in tp_pm_configure()
68 t1_write_reg_4(adapter, A_TP_PM_RX_PG_SIZE, p->pm_rx_pg_size); in tp_pm_configure()
69 t1_write_reg_4(adapter, A_TP_PM_RX_MAX_PGS, p->pm_rx_num_pgs); in tp_pm_configure()
70 t1_write_reg_4(adapter, A_TP_PM_TX_PG_SIZE, p->pm_tx_pg_size); in tp_pm_configure()
71 t1_write_reg_4(adapter, A_TP_PM_TX_MAX_PGS, p->pm_tx_num_pgs); in tp_pm_configure()
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H A Dvsc7326.c55 static void vsc_read(adapter_t *adapter, u32 addr, u32 *val) in vsc_read() argument
60 MAC_LOCK(adapter->mac_lock); in vsc_read()
61 (void) t1_tpi_read(adapter, (addr << 2) + 4, &vlo); in vsc_read()
64 (void) t1_tpi_read(adapter, (REG_LOCAL_STATUS << 2) + 4, &vlo); in vsc_read()
65 (void) t1_tpi_read(adapter, REG_LOCAL_STATUS << 2, &vhi); in vsc_read()
72 (void) t1_tpi_read(adapter, (REG_LOCAL_DATA << 2) + 4, &vlo); in vsc_read()
73 (void) t1_tpi_read(adapter, REG_LOCAL_DATA << 2, &vhi); in vsc_read()
80 MAC_UNLOCK(adapter->mac_lock); in vsc_read()
83 static void vsc_write(adapter_t *adapter, u32 addr, u32 data) in vsc_write() argument
85 MAC_LOCK(adapter->mac_lock); in vsc_write()
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H A Dulp.c33 adapter_t *adapter; member
46 if (t1_is_asic(ulp->adapter)) { in t1_ulp_intr_enable()
47 u32 pl_intr = t1_read_reg_4(ulp->adapter, A_PL_ENABLE); in t1_ulp_intr_enable()
49 t1_write_reg_4(ulp->adapter, A_ULP_INT_ENABLE, ULP_INTR_MASK); in t1_ulp_intr_enable()
50 t1_write_reg_4(ulp->adapter, A_PL_ENABLE, in t1_ulp_intr_enable()
57 if (t1_is_asic(ulp->adapter)) { in t1_ulp_intr_clear()
58 t1_write_reg_4(ulp->adapter, A_PL_CAUSE, F_PL_INTR_ULP); in t1_ulp_intr_clear()
59 t1_write_reg_4(ulp->adapter, A_ULP_INT_CAUSE, 0xffffffff); in t1_ulp_intr_clear()
65 if (t1_is_asic(ulp->adapter)) { in t1_ulp_intr_disable()
66 u32 pl_intr = t1_read_reg_4(ulp->adapter, A_PL_ENABLE); in t1_ulp_intr_disable()
[all …]
H A Dpm3393.c97 (void) t1_tpi_read(cmac->adapter, OFFSET(reg), data32); in pmread()
103 (void) t1_tpi_write(cmac->adapter, OFFSET(reg), data32); in pmwrite()
161 (void) t1_tpi_read(cmac->adapter, A_ELMER0_INT_ENABLE, &elmer); in pm3393_interrupt_enable()
163 (void) t1_tpi_write(cmac->adapter, A_ELMER0_INT_ENABLE, elmer); in pm3393_interrupt_enable()
167 pl_intr = t1_read_reg_4(cmac->adapter, A_PL_ENABLE); in pm3393_interrupt_enable()
169 t1_write_reg_4(cmac->adapter, A_PL_ENABLE, pl_intr); in pm3393_interrupt_enable()
200 (void) t1_tpi_read(cmac->adapter, A_ELMER0_INT_ENABLE, &elmer); in pm3393_interrupt_disable()
202 (void) t1_tpi_write(cmac->adapter, A_ELMER0_INT_ENABLE, elmer); in pm3393_interrupt_disable()
243 (void) t1_tpi_read(cmac->adapter, A_ELMER0_INT_CAUSE, &elmer); in pm3393_interrupt_clear()
245 (void) t1_tpi_write(cmac->adapter, A_ELMER0_INT_CAUSE, elmer); in pm3393_interrupt_clear()
[all …]
H A Dcommon.h206 static inline int t1_is_asic(const adapter_t *adapter) in t1_is_asic() argument
208 return adapter->params.is_asic; in t1_is_asic()
211 static inline int adapter_matches_type(const adapter_t *adapter, in adapter_matches_type() argument
214 return adapter->params.chip_version == version && in adapter_matches_type()
215 adapter->params.chip_revision == revision; in adapter_matches_type()
222 static inline int vlan_tso_capable(const adapter_t *adapter) in vlan_tso_capable() argument
224 return !t1_is_T1B(adapter); in vlan_tso_capable()
227 #define for_each_port(adapter, iter) \ argument
228 for (iter = 0; iter < (adapter)->params.nports; ++iter)
230 #define board_info(adapter) ((adapter)->params.brd_info) argument
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H A Dmy3126.c47 if (!is_T2(cphy->adapter)) in my3126_interrupt_enable()
50 (void) t1_tpi_read(cphy->adapter, A_ELMER0_GPO, &cphy->elmer_gpo); in my3126_interrupt_enable()
58 if (is_T2(cphy->adapter)) in my3126_interrupt_disable()
77 adapter_t *adapter; in my3126_interrupt_handler() local
80 if (!is_T2(cphy->adapter)) in my3126_interrupt_handler()
83 adapter = cphy->adapter; in my3126_interrupt_handler()
90 link_changed(adapter, 0); in my3126_interrupt_handler()
99 (void) t1_tpi_write(adapter, OFFSET(SUNI1x10GEXP_REG_MSTAT_CONTROL), in my3126_interrupt_handler()
101 (void) t1_tpi_read(adapter, in my3126_interrupt_handler()
103 (void) t1_tpi_read(adapter, in my3126_interrupt_handler()
[all …]
H A Dch_mac.c84 if (t1_is_asic(mac->adapter)) { in mac_intr_enable()
92 mac_intr = t1_read_reg_4(mac->adapter, A_PL_ENABLE); in mac_intr_enable()
94 t1_write_reg_4(mac->adapter, A_PL_ENABLE, mac_intr); in mac_intr_enable()
96 mac_intr = t1_read_reg_4(mac->adapter, in mac_intr_enable()
99 t1_write_reg_4(mac->adapter, in mac_intr_enable()
110 if (t1_is_asic(mac->adapter)) { in mac_intr_disable()
118 mac_intr = t1_read_reg_4(mac->adapter, A_PL_ENABLE); in mac_intr_disable()
120 t1_write_reg_4(mac->adapter, A_PL_ENABLE, mac_intr); in mac_intr_disable()
122 mac_intr = t1_read_reg_4(mac->adapter, in mac_intr_disable()
125 t1_write_reg_4(mac->adapter, in mac_intr_disable()
[all …]
H A Dixf1010.c169 (void) t1_tpi_read(mac->adapter, REG_PORT_ENABLE, &val); in disable_port()
171 (void) t1_tpi_write(mac->adapter, REG_PORT_ENABLE, val); in disable_port()
175 (void) t1_tpi_read((mac)->adapter, MACREG(mac, REG_##name), &val); \
238 (void) t1_tpi_write(mac->adapter, MACREG(mac, REG_MACADDR_LOW), addr_lo); in mac_set_address()
239 (void) t1_tpi_write(mac->adapter, MACREG(mac, REG_MACADDR_HIGH), addr_hi); in mac_set_address()
247 (void) t1_tpi_read(mac->adapter, MACREG(mac, REG_MACADDR_LOW), &addr_lo); in mac_get_address()
248 (void) t1_tpi_read(mac->adapter, MACREG(mac, REG_MACADDR_HIGH), &addr_hi); in mac_get_address()
269 adapter_t *adapter = mac->adapter; in mac_set_rx_mode() local
273 (void) t1_tpi_read(adapter, MACREG(mac, REG_RX_FILTER), &val); in mac_set_rx_mode()
281 (void) t1_tpi_write(adapter, MACREG(mac, REG_RX_FILTER), new_mode); in mac_set_rx_mode()
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H A Dvsc7321.c66 static void vsc_read(adapter_t *adapter, u32 addr, u32 *val) in vsc_read() argument
70 (void) t1_tpi_read(adapter, (addr << 2) + 4, &vlo); in vsc_read()
73 (void) t1_tpi_read(adapter, (REG_LOCAL_STATUS << 2) + 4, &vlo); in vsc_read()
74 (void) t1_tpi_read(adapter, REG_LOCAL_STATUS << 2, &vhi); in vsc_read()
78 (void) t1_tpi_read(adapter, (REG_LOCAL_DATA << 2) + 4, &vlo); in vsc_read()
79 (void) t1_tpi_read(adapter, REG_LOCAL_DATA << 2, &vhi); in vsc_read()
84 static void vsc_write(adapter_t *adapter, u32 addr, u32 data) in vsc_write() argument
86 (void) t1_tpi_write(adapter, (addr << 2) + 4, data & 0xFFFF); in vsc_write()
87 (void) t1_tpi_write(adapter, addr << 2, (data >> 16) & 0xFFFF); in vsc_write()
91 static void vsc7321_full_reset(adapter_t* adapter) in vsc7321_full_reset() argument
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H A Dmc5.c107 adapter_t *adapter; member
127 static int mc5_cmd_write(adapter_t *adapter, u32 cmd) in mc5_cmd_write() argument
129 t1_write_reg_4(adapter, A_MC5_DBGI_REQ_CMD, cmd); in mc5_cmd_write()
130 return t1_wait_op_done(adapter, A_MC5_DBGI_RSP_STATUS, in mc5_cmd_write()
143 t1_write_reg_4(mc5->adapter, A_MC5_ROUTING_TABLE_INDEX, rtbl_base); in set_tcam_rtbl_base()
149 return t1_read_reg_4(mc5->adapter, A_MC5_ROUTING_TABLE_INDEX); in t1_mc5_get_tcam_rtbl_base()
163 t1_write_reg_4(mc5->adapter, A_MC5_SERVER_INDEX, server_base); in set_tcam_server_base()
169 return t1_read_reg_4(mc5->adapter, A_MC5_SERVER_INDEX); in t1_mc5_get_tcam_server_base()
180 static inline void dbgi_wr_addr3(adapter_t *adapter, u32 v1, u32 v2, u32 v3) in dbgi_wr_addr3() argument
182 t1_write_reg_4(adapter, A_MC5_DBGI_REQ_ADDR0, v1); in dbgi_wr_addr3()
[all …]
/titanic_44/usr/src/uts/common/io/ntxn/
H A Dniu.c54 static int phy_lock(struct unm_adapter_s *adapter) in phy_lock() argument
61 adapter->unm_nic_pci_read_immediate(adapter, in phy_lock()
70 adapter->unm_crb_writelit_adapter(adapter, UNM_PHY_LOCK_ID, in phy_lock()
76 phy_unlock(struct unm_adapter_s *adapter) in phy_unlock() argument
81 adapter->unm_nic_pci_read_immediate(adapter, in phy_unlock()
99 unm_niu_gbe_phy_read(struct unm_adapter_s *adapter, long reg, in unm_niu_gbe_phy_read() argument
102 long phy = adapter->physical_port; in unm_niu_gbe_phy_read()
112 if (phy_lock(adapter) != 0) in unm_niu_gbe_phy_read()
119 adapter->unm_nic_hw_read_wx(adapter, UNM_NIU_GB_MAC_CONFIG_0(0), in unm_niu_gbe_phy_read()
128 adapter->unm_nic_hw_write_wx(adapter, in unm_niu_gbe_phy_read()
[all …]
H A Dunm_gem.c73 extern int unm_register_mac(unm_adapter *adapter);
74 extern void unm_fini_kstats(unm_adapter* adapter);
75 extern void unm_nic_remove(unm_adapter *adapter);
140 check_hw_init(struct unm_adapter_s *adapter) in check_hw_init() argument
145 adapter->unm_nic_hw_read_wx(adapter, UNM_CAM_RAM(0x1fc), &val, 4); in check_hw_init()
148 adapter->unm_nic_hw_read_wx(adapter, UNM_ROMUSB_GLB_SW_RESET, in check_hw_init()
153 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { in check_hw_init()
155 adapter->unm_nic_pci_write_normalize(adapter, in check_hw_init()
157 adapter->unm_nic_pci_write_normalize(adapter, in check_hw_init()
166 unm_get_flash_block(unm_adapter *adapter, int base, int size, uint32_t *buf) in unm_get_flash_block() argument
[all …]
H A Dunm_ndd.c185 unm_param_register(unm_adapter *adapter) in unm_param_register() argument
195 dip = adapter->dip; in unm_param_register()
196 nddpp = &adapter->nd_data_p; in unm_param_register()
199 if (adapter->ahw.board_type == UNM_NIC_XGBE) in unm_param_register()
210 ndp = &adapter->nd_params[tmplp->ndp_info]; in unm_param_register()
248 if (adapter->ahw.board_type == UNM_NIC_XGBE) { in unm_param_register()
262 unm_nd_init(unm_adapter *adapter) in unm_nd_init() argument
273 if (unm_param_register(adapter) != DDI_SUCCESS) in unm_nd_init()
284 dip = adapter->dip; in unm_nd_init()
291 adapter->param_adv_autoneg = 1; in unm_nd_init()
[all …]
H A Dunm_nic_main.c97 extern int create_rxtx_rings(unm_adapter *adapter);
98 extern void destroy_rxtx_rings(unm_adapter *adapter);
100 static void unm_post_rx_buffers_nodb(struct unm_adapter_s *adapter,
102 static mblk_t *unm_process_rcv(unm_adapter *adapter, statusDesc_t *desc);
104 static int unm_process_cmd_ring(struct unm_adapter_s *adapter);
106 static int unm_nic_do_ioctl(unm_adapter *adapter, queue_t *q, mblk_t *mp);
107 static void unm_nic_ioctl(struct unm_adapter_s *adapter, int cmd, queue_t *q,
125 unm_pci_alloc_consistent(unm_adapter *adapter, in unm_pci_alloc_consistent() argument
139 err = ddi_dma_alloc_handle(adapter->dip, in unm_pci_alloc_consistent()
140 &adapter->gc_dma_attr_desc, in unm_pci_alloc_consistent()
[all …]
H A Dunm_nic_hw.c307 crb_win_lock(struct unm_adapter_s *adapter) in crb_win_lock() argument
314 adapter->unm_nic_hw_read_wx(adapter, in crb_win_lock()
320 adapter->name, adapter->instance); in crb_win_lock()
329 adapter->unm_crb_writelit_adapter(adapter, UNM_CRB_WIN_LOCK_ID, in crb_win_lock()
330 adapter->portnum); in crb_win_lock()
334 crb_win_unlock(struct unm_adapter_s *adapter) in crb_win_unlock() argument
338 adapter->unm_nic_hw_read_wx(adapter, UNM_PCIE_REG(PCIE_SEM7_UNLOCK), in crb_win_unlock()
346 unm_nic_pci_change_crbwindow_128M(unm_adapter *adapter, uint32_t wndw) in unm_nic_pci_change_crbwindow_128M() argument
352 if (adapter->curr_window == wndw) { in unm_nic_pci_change_crbwindow_128M()
364 offset = PCI_OFFSET_SECOND_RANGE(adapter, in unm_nic_pci_change_crbwindow_128M()
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H A Dunm_nic_isr.c55 unm_nic_isr_other(struct unm_adapter_s *adapter) in unm_nic_isr_other() argument
57 u32 portno = adapter->portnum; in unm_nic_isr_other()
58 u32 val, linkup, qg_linksup = adapter->ahw.linkup; in unm_nic_isr_other()
60 UNM_READ_LOCK(&adapter->adapter_lock); in unm_nic_isr_other()
61 adapter->unm_nic_hw_read_wx(adapter, CRB_XG_STATE, &val, 4); in unm_nic_isr_other()
62 UNM_READ_UNLOCK(&adapter->adapter_lock); in unm_nic_isr_other()
64 linkup = 1 & (val >> adapter->physical_port); in unm_nic_isr_other()
65 adapter->ahw.linkup = linkup; in unm_nic_isr_other()
70 mac_link_update(adapter->mach, linkup); in unm_nic_isr_other()
72 unm_nic_set_link_parameters(adapter); in unm_nic_isr_other()
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H A Dunm_nic_init.c161 rom_lock(unm_adapter *adapter) in rom_lock() argument
168 unm_nic_read_w0(adapter, UNM_PCIE_REG(PCIE_SEM2_LOCK), &done); in rom_lock()
173 adapter->name, adapter->instance, done, timeout); in rom_lock()
178 unm_nic_reg_write(adapter, UNM_ROM_LOCK_ID, ROM_LOCK_DRIVER); in rom_lock()
183 rom_unlock(unm_adapter *adapter) in rom_unlock() argument
188 unm_nic_read_w0(adapter, UNM_PCIE_REG(PCIE_SEM2_UNLOCK), &val); in rom_unlock()
192 wait_rom_done(unm_adapter *adapter) in wait_rom_done() argument
198 unm_nic_reg_read(adapter, UNM_ROMUSB_GLB_STATUS, &done); in wait_rom_done()
211 do_rom_fast_read(unm_adapter *adapter, int addr, int *valp) in do_rom_fast_read() argument
213 unm_nic_reg_write(adapter, UNM_ROMUSB_ROM_ADDRESS, addr); in do_rom_fast_read()
[all …]
H A Dunm_nic_ctx.c114 netxen_api_lock(struct unm_adapter_s *adapter) in netxen_api_lock() argument
120 unm_nic_read_w0(adapter, in netxen_api_lock()
135 unm_nic_reg_write(adapter, NETXEN_API_LOCK_ID, NX_OS_API_LOCK_DRIVER); in netxen_api_lock()
141 netxen_api_unlock(struct unm_adapter_s *adapter) in netxen_api_unlock() argument
146 unm_nic_read_w0(adapter, in netxen_api_unlock()
151 netxen_poll_rsp(struct unm_adapter_s *adapter) in netxen_poll_rsp() argument
163 adapter->unm_nic_hw_read_wx(adapter, NX_CDRP_CRB_OFFSET, in netxen_poll_rsp()
173 netxen_issue_cmd(struct unm_adapter_s *adapter, in netxen_issue_cmd() argument
183 if (netxen_api_lock(adapter)) in netxen_issue_cmd()
186 unm_nic_reg_write(adapter, NX_SIGN_CRB_OFFSET, in netxen_issue_cmd()
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H A Dunm_nic.h106 #define CRB_NORMALIZE(adapter, reg) \ argument
107 (void *)(unsigned long)(pci_base_offset(adapter, CRB_NORMAL(reg)))
109 #define DB_NORMALIZE(adapter, off) \ argument
110 (void *)((unsigned long)adapter->ahw.db_base + (off))
125 ddi_put32(adapter->db_handle, (uint32_t *)(ADDRESS), (DATA))
132 ddi_get8(adapter->regs_handle, (uint8_t *)(ADDRESS))
134 ddi_get16(adapter->regs_handle, (uint16_t *)(ADDRESS))
136 ddi_get32(adapter->regs_handle, (uint32_t *)(ADDRESS))
138 ddi_get64(adapter->regs_handle, (uint64_t *)(ADDRESS))
141 ddi_put8(adapter->regs_handle, (uint8_t *)(ADDRESS), (DATA))
[all …]
/titanic_44/usr/src/uts/common/io/cxgbe/common/
H A Dcommon.h301 #define for_each_port(adapter, iter) \ argument
302 for (iter = 0; iter < (adapter)->params.nports; ++iter)
304 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
307 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
310 int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
313 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
316 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
322 void t4_intr_enable(struct adapter *adapter);
323 void t4_intr_disable(struct adapter *adapter);
324 void t4_intr_clear(struct adapter *adapter);
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H A Dt4_hw.c45 t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, in t4_wait_op_done_val() argument
52 u32 val = t4_read_reg(adapter, reg); in t4_wait_op_done_val()
82 t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask, u32 val) in t4_set_reg_field() argument
84 u32 v = t4_read_reg(adapter, addr) & ~mask; in t4_set_reg_field()
86 t4_write_reg(adapter, addr, v | val); in t4_set_reg_field()
87 (void) t4_read_reg(adapter, addr); /* flush */ in t4_set_reg_field()
103 t4_read_indirect(struct adapter *adap, unsigned int addr_reg, in t4_read_indirect()
127 t4_write_indirect(struct adapter *adap, unsigned int addr_reg, in t4_write_indirect()
141 get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit, u32 mbox_addr) in get_mbox_rpl()
151 fw_asrt(struct adapter *adap, u32 mbox_addr) in fw_asrt()
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