/titanic_44/usr/src/uts/intel/ia32/sys/ |
H A D | asm_linkage.h | 59 #define _CONST(const) [const] macro 60 #define _BITNOT(const) -1!_CONST(const) 61 #define _MUL(a, b) _CONST(a \* b) 72 #define _CONST(const) (const) 73 #define _BITNOT(const) ~_CONST(const) 74 #define _MUL(a, b) _CONST(a * b) 119 subq $_CONST(_MUL(XMM_SIZE, nreg)), %rsp; \ 123 addq $_CONST(_MUL(XMM_SIZE, nreg)), %rsp 128 subl $_CONST(_MUL(XMM_SIZE, nreg) + XMM_ALIGN), %esp; \ 134 addl $_CONST(_MUL(XMM_SIZE, nreg) + XMM_ALIGN), %esp;
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/titanic_44/usr/src/uts/intel/amd64/ml/ |
H A D | mach_offsets.in | 123 \#define LABEL_RBP _CONST(_MUL(2, LABEL_VAL_INCR) + LABEL_VAL) 124 \#define LABEL_RBX _CONST(_MUL(3, LABEL_VAL_INCR) + LABEL_VAL) 125 \#define LABEL_R12 _CONST(_MUL(4, LABEL_VAL_INCR) + LABEL_VAL) 126 \#define LABEL_R13 _CONST(_MUL(5, LABEL_VAL_INCR) + LABEL_VAL) 127 \#define LABEL_R14 _CONST(_MUL(6, LABEL_VAL_INCR) + LABEL_VAL) 128 \#define LABEL_R15 _CONST(_MUL(7, LABEL_VAL_INCR) + LABEL_VAL) 129 \#define T_RBP _CONST(T_LABEL + LABEL_RBP) 130 \#define T_RBX _CONST(T_LABEL + LABEL_RBX) 131 \#define T_R12 _CONST(T_LABEL + LABEL_R12) 132 \#define T_R13 _CONST(T_LABEL + LABEL_R13) [all …]
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/titanic_44/usr/src/uts/intel/kdi/ |
H A D | kdi_offsets.in | 81 \#define DRADDR_IDX(num) _CONST(_MUL(num, DR_ADDR_INCR)) 82 \#define DRADDR_OFF(num) _CONST(DRADDR_IDX(num) + DR_ADDR) 83 \#define KRS_DROFF(num) _CONST(DRADDR_OFF(num) + KRS_DR) 84 \#define REG_OFF(reg) _CONST(_CONST(reg) << REG_SHIFT) 85 \#define KDIREG_OFF(reg) _CONST(_MUL(KREG_SIZE, reg) + KRS_GREGS)
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/titanic_44/usr/src/uts/i86pc/ml/ |
H A D | mach_offsets.in | 117 \#define LABEL_EBP _CONST(_MUL(2, LABEL_VAL_INCR) + LABEL_VAL) 118 \#define LABEL_EBX _CONST(_MUL(3, LABEL_VAL_INCR) + LABEL_VAL) 119 \#define LABEL_ESI _CONST(_MUL(4, LABEL_VAL_INCR) + LABEL_VAL) 120 \#define LABEL_EDI _CONST(_MUL(5, LABEL_VAL_INCR) + LABEL_VAL) 121 \#define T_EBP _CONST(T_LABEL + LABEL_EBP) 122 \#define T_EBX _CONST(T_LABEL + LABEL_EBX) 123 \#define T_ESI _CONST(T_LABEL + LABEL_ESI) 124 \#define T_EDI _CONST(T_LABEL + LABEL_EDI)
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H A D | comm_page.s | 65 .fill 1, 4, _CONST(TSC_RDTSC_CPUID) 83 .fill _CONST(NCPU), 8, 0 86 .fill _CONST(COMM_PAGE_SIZE - COMM_PAGE_S_SIZE), 1, 0
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H A D | cpr_wakecode.s | 302 D16 orl $_CONST(CR0_PE|CR0_WP|CR0_AM), %eax 487 D16 movl $_CONST(COM1+LCR), %edx 491 D16 movl $_CONST(COM1+DLL), %edx / divisor latch lsb 495 D16 movl $_CONST(COM1+DLH), %edx / divisor latch hsb 499 D16 movl $_CONST(COM1+LCR), %edx / select COM1 500 D16 movb $_CONST(STOP1|BITS8), %al / 1 stop bit, 8bit word len 503 D16 movl $_CONST(COM1+MCR), %edx / select COM1 504 D16 movb $_CONST(RTS|DTR), %al / data term ready & req to send 508 D16 movl $_CONST(COM2+LCR), %edx 512 D16 movl $_CONST(COM2+DLL), %edx / divisor latch lsb [all …]
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H A D | fast_trap_asm.s | 146 movl _CONST(4 + 0)(%esp), %eax 147 movl _CONST(4 + CLONGSIZE)(%esp), %edx 148 addl $_CONST(4 + TIMESPEC_SIZE), %esp
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H A D | offsets.in | 144 \#define LABEL_SP _CONST(LABEL_VAL + LABEL_VAL_INCR) 145 \#define T_PC _CONST(T_LABEL + LABEL_PC) 146 \#define T_SP _CONST(T_LABEL + LABEL_SP) 165 \#define LWP_ACCT_USER _CONST(LWP_MS_ACCT + _MUL(LMS_USER, LWP_MS_ACCT_INCR)) 166 \#define LWP_ACCT_SYSTEM _CONST(LWP_MS_ACCT + _MUL(LMS_SYSTEM, LWP_MS_ACCT_INCR)) 217 \#define CPU_INTR_ACTV_REF _CONST(CPU_INTR_ACTV + 2)
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H A D | syscall_asm.s | 153 movl _CONST(_MUL(callback_id, CPTRSIZE))(%ebx), %ebx ;\ 298 andb $_CONST(0xffff - PS_C), REGOFF_EFL(%esp) 348 #define SYS_DROP _CONST(_MUL(MAXSYSARGS, 4))
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H A D | fb_swtch_src.s | 274 orl $_CONST(CR0_PG | CR0_WP | CR0_AM), %eax
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H A D | locore.s | 175 addq $_CONST(DEFAULTSTKSZ - REGSIZE), %rsp 205 orq $_CONST(CR0_WP|CR0_AM), %rax 301 orl $_CONST(CR0_WP|CR0_AM), %eax
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H A D | syscall_asm_amd64.s | 196 movq _CONST(_MUL(callback_id, CPTRSIZE))(%r15), %r15 ;\ 240 andb $_CONST(0xffff - PS_C), REGOFF_RFL(%rsp)
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/titanic_44/usr/src/uts/intel/ia32/ml/ |
H A D | ddi_i86_asm.s | 280 cmpl $_CONST(DDI_ACCATTR_IO_SPACE|DDI_ACCATTR_DIRECT), %edx 287 cmpl $_CONST(DDI_ACCATTR_CPU_VADDR|DDI_ACCATTR_DIRECT), %edx 310 cmpl $_CONST(DDI_ACCATTR_IO_SPACE|DDI_ACCATTR_DIRECT), %ecx 317 cmpl $_CONST(DDI_ACCATTR_CPU_VADDR|DDI_ACCATTR_DIRECT), %ecx 342 cmpl $_CONST(DDI_ACCATTR_IO_SPACE|DDI_ACCATTR_DIRECT), %edx 349 cmpl $_CONST(DDI_ACCATTR_CPU_VADDR|DDI_ACCATTR_DIRECT), %edx 372 cmpl $_CONST(DDI_ACCATTR_IO_SPACE|DDI_ACCATTR_DIRECT), %ecx 379 cmpl $_CONST(DDI_ACCATTR_CPU_VADDR|DDI_ACCATTR_DIRECT), %ecx 404 cmpl $_CONST(DDI_ACCATTR_IO_SPACE|DDI_ACCATTR_DIRECT), %edx 410 cmpl $_CONST(DDI_ACCATTR_CPU_VADDR|DDI_ACCATTR_DIRECT), %edx [all …]
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H A D | float.s | 295 movl $_CONST(FPU_VALID|FPU_EN), FPU_CTX_FPU_FLAGS(%rdi) 323 movl $_CONST(FPU_VALID|FPU_EN), FPU_CTX_FPU_FLAGS(%rdi) 354 movl $_CONST(FPU_VALID|FPU_EN), FPU_CTX_FPU_FLAGS(%eax) 367 movl $_CONST(FPU_VALID|FPU_EN), FPU_CTX_FPU_FLAGS(%eax) 386 movl $_CONST(FPU_VALID|FPU_EN), FPU_CTX_FPU_FLAGS(%ecx)
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H A D | sseblk.s | 313 movl $_CONST(32 - 1), %ecx 352 movl $_CONST(32 - 1), %ecx
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H A D | exception.s | 1237 pushq $_CONST(_MUL(T_FASTTRAP, GATE_DESC_SIZE) + 2) 1263 pushl $_CONST(_MUL(T_FASTTRAP, GATE_DESC_SIZE) + 2)
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/titanic_44/usr/src/uts/i86xpv/ml/ |
H A D | hyperevent.s | 103 addq $_CONST(_MUL(4, CLONGSIZE)), %rsp 154 addl $_CONST(_MUL(4, CLONGSIZE)), %esp /* see comment for 64-bit */
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/titanic_44/usr/src/lib/commpage/amd64/ |
H A D | cp_subr.s | 241 shrdq $_CONST(32 - NSEC_SHIFT), %rdx, %rax 351 movq _CONST(CP_HRESTIME + CP_HRESTIME_INCR)(%rdi), %r10
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/titanic_44/usr/src/cmd/mdb/intel/kmdb/ |
H A D | kmdb_context_off.in | 35 \#define UC_GREG(name) _CONST(UC_GREGS + _MUL(name, UC_GREGS_INCR))
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/titanic_44/usr/src/uts/i86pc/sys/ |
H A D | machparam.h | 100 #define MMU_PAGEOFFSET _CONST(MMU_PAGESIZE-1) /* assembler lameness */
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/titanic_44/usr/src/lib/brand/shared/brand/i386/ |
H A D | handler.s | 32 pushl $_CONST(. - brand_handler_table); \
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/titanic_44/usr/src/uts/i86pc/dboot/ |
H A D | dboot_grub.s | 274 orl $_CONST(CR0_PG | CR0_WP | CR0_AM), %eax
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/titanic_44/usr/src/lib/brand/shared/brand/amd64/ |
H A D | handler.s | 31 pushq $_CONST(. - brand_handler_table); \
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/titanic_44/usr/src/uts/intel/kdi/ia32/ |
H A D | kdi_asm.s | 565 movl %edx, _CONST(MSR_VAL + 4)(%ebx)
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/titanic_44/usr/src/uts/intel/kdi/amd64/ |
H A D | kdi_asm.s | 561 movl %edx, _CONST(MSR_VAL + 4)(%rbx)
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