Searched refs:Y2_CLK_DIV_DIS (Results 1 – 2 of 2) sorted by relevance
793 #define Y2_CLK_DIV_DIS BIT(0) /* Disable Core Clock Division */ macro
576 CSR_WRITE_4(dev, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); in yge_phy_power()