Searched refs:V_MI0_CLK_DIV (Results 1 – 2 of 2) sorted by relevance
80 #define V_MI0_CLK_DIV(x) ((x) << S_MI0_CLK_DIV) macro
270 t1_write_reg_4(adapter, A_MI0_CLK, V_MI0_CLK_DIV(3)); in fpga_mdio_init()