Searched refs:UNM_CRB_DDR_NET (Results 1 – 4 of 4) sorted by relevance
451 #define UNM_CRB_DDR_NET UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_MN) macro1762 #define UNM_MIU_MN_CONTROL (UNM_CRB_DDR_NET + MIU_CONTROL)1763 #define UNM_MIU_MN_TAG (UNM_CRB_DDR_NET + MIU_TAG)1764 #define UNM_MIU_MN_TEST_AGT_ADDR_LO (UNM_CRB_DDR_NET + MIU_TEST_AGT_ADDR_LO)1765 #define UNM_MIU_MN_TEST_AGT_ADDR_HI (UNM_CRB_DDR_NET + MIU_TEST_AGT_ADDR_HI)1766 #define UNM_MIU_MN_TEST_AGT_WRDATA_LO (UNM_CRB_DDR_NET + MIU_TEST_AGT_WRDATA_LO)1767 #define UNM_MIU_MN_TEST_AGT_WRDATA_HI (UNM_CRB_DDR_NET + MIU_TEST_AGT_WRDATA_HI)1768 #define UNM_MIU_MN_TEST_AGT_CTRL (UNM_CRB_DDR_NET + MIU_TEST_AGT_CTRL)1769 #define UNM_MIU_MN_TEST_AGT_RDDATA_LO (UNM_CRB_DDR_NET + MIU_TEST_AGT_RDDATA_LO)1770 #define UNM_MIU_MN_TEST_AGT_RDDATA_HI (UNM_CRB_DDR_NET + MIU_TEST_AGT_RDDATA_HI)
1256 mem_crb = (uptr_t)(pci_base_offset(adapter, UNM_CRB_DDR_NET)); in unm_nic_pci_mem_write_128M()1350 mem_crb = (uptr_t)(pci_base_offset(adapter, UNM_CRB_DDR_NET)); in unm_nic_pci_mem_read_128M()1436 mem_crb = UNM_CRB_DDR_NET; in unm_nic_pci_mem_write_2M()1542 mem_crb = UNM_CRB_DDR_NET; in unm_nic_pci_mem_read_2M()
776 mem_crb = UNM_CRB_DDR_NET; in ql_8021_pci_mem_read_2M()886 mem_crb = UNM_CRB_DDR_NET; in ql_8021_pci_mem_write_2M()1449 if ((off & 0x0ff00000) == UNM_CRB_DDR_NET) { in ql_8021_pinit_from_rom()
586 #define UNM_CRB_DDR_NET (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_MN)) macro