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Searched refs:REG_SET_BIT (Results 1 – 5 of 5) sorted by relevance

/titanic_44/usr/src/uts/common/io/arn/
H A Darn_calib.c244 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), in ath9k_hw_setup_calibration()
482 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), in ath9k_hw_iqcalibrate()
654 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, in ath9k_hw_start_nfcal()
656 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, in ath9k_hw_start_nfcal()
658 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); in ath9k_hw_start_nfcal()
702 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); in ath9k_hw_loadnf()
H A Darn_hw.c1152 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, in ath9k_hw_init_chain_masks()
1174 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, in ath9k_hw_init_chain_masks()
1344 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); in ath9k_hw_override_ini()
1625 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); in ath9k_hw_set_operating_mode()
2471 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, in ath9k_hw_reset()
2838 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); in ath9k_set_power_sleep()
2853 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); in ath9k_set_power_network_sleep()
2882 REG_SET_BIT(ah, AR_RTC_RESET, in ath9k_hw_set_power_awake()
2885 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, in ath9k_hw_set_power_awake()
2894 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, in ath9k_hw_set_power_awake()
[all …]
H A Darn_mac.c220 REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); in ath9k_hw_stoptxdma()
230 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); in ath9k_hw_stoptxdma()
1039 REG_SET_BIT(ah, AR_DIAG_SW, in ath9k_hw_setrxabort()
1088 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS); in ath9k_hw_stoppcurecv()
H A Darn_ani.c131 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, in ath9k_hw_ani_control()
H A Darn_ath9k.h625 #define REG_SET_BIT(_a, _r, _f) \ macro