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Searched refs:REG_CLR_BIT (Results 1 – 5 of 5) sorted by relevance

/titanic_44/usr/src/uts/common/io/arn/
H A Darn_mac.c233 REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); in ath9k_hw_stoptxdma()
248 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); in ath9k_hw_stoptxdma()
1044 REG_CLR_BIT(ah, AR_DIAG_SW, in ath9k_hw_setrxabort()
1056 REG_CLR_BIT(ah, AR_DIAG_SW, in ath9k_hw_setrxabort()
1082 REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); in ath9k_hw_startpcureceive()
H A Darn_hw.c1620 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); in ath9k_hw_set_operating_mode()
2002 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, in ath9k_hw_9280_spur_mitigate()
2006 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, in ath9k_hw_9280_spur_mitigate()
2840 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, in ath9k_set_power_sleep()
2845 REG_CLR_BIT(ah, (uint16_t)(AR_RTC_RESET), in ath9k_set_power_sleep()
2861 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, in ath9k_set_power_network_sleep()
2907 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); in ath9k_hw_set_power_awake()
3273 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); in ath9k_hw_set_interrupts()
3845 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2, in ath9k_enable_rfkill()
H A Darn_calib.c698 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, in ath9k_hw_loadnf()
700 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, in ath9k_hw_loadnf()
H A Darn_ani.c134 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, in ath9k_hw_ani_control()
H A Darn_ath9k.h627 #define REG_CLR_BIT(_a, _r, _f) \ macro