Home
last modified time | relevance | path

Searched refs:RD32_IO_REG (Results 1 – 7 of 7) sorted by relevance

/titanic_44/usr/src/uts/common/io/fibre-channel/fca/qlc/
H A Dql_ioctl.c882 RD32_IO_REG(ha, ctrl_status) | ISP_FLASH_ENABLE); in ql_24xx_load_nvram()
883 RD32_IO_REG(ha, ctrl_status); /* PCI Posting. */ in ql_24xx_load_nvram()
910 RD32_IO_REG(ha, ctrl_status) & ~ISP_FLASH_ENABLE); in ql_24xx_load_nvram()
911 RD32_IO_REG(ha, ctrl_status); /* PCI Posting. */ in ql_24xx_load_nvram()
H A Dql_api.c2273 stat = RD32_IO_REG(ha, risc2host); in ql_quiesce()
11492 RD32_IO_REG(ha, ctrl_status) | FLASH_NVRAM_ACCESS_ERROR); in ql_24xx_read_flash()
11498 if (RD32_IO_REG(ha, flash_address) & FLASH_DATA_FLAG) { in ql_24xx_read_flash()
11507 } else if (RD32_IO_REG(ha, ctrl_status) & FLASH_NVRAM_ACCESS_ERROR) { in ql_24xx_read_flash()
11512 *bp = RD32_IO_REG(ha, flash_data); in ql_24xx_read_flash()
11547 RD32_IO_REG(ha, ctrl_status) | FLASH_NVRAM_ACCESS_ERROR); in ql_24xx_write_flash()
11550 RD32_IO_REG(ha, flash_data); /* PCI Posting. */ in ql_24xx_write_flash()
11555 if ((RD32_IO_REG(ha, flash_address) & FLASH_DATA_FLAG) == 0) { in ql_24xx_write_flash()
11572 } else if (RD32_IO_REG(ha, ctrl_status) & FLASH_NVRAM_ACCESS_ERROR) { in ql_24xx_write_flash()
11623 RD32_IO_REG(ha, ctrl_status) | ISP_FLASH_ENABLE); in ql_24xx_unprotect_flash()
[all …]
H A Dql_init.c3550 RD32_IO_REG(ha, ictrl); in ql_reset_chip()
3713 if ((RD32_IO_REG(ha, ctrl_status) & DMA_ACTIVE) == 0) { in ql_reset_24xx_chip()
3724 stat = RD32_IO_REG(ha, risc2host); in ql_reset_24xx_chip()
3750 if ((RD32_IO_REG(ha, ctrl_status) & ISP_RESET) == 0) { in ql_reset_24xx_chip()
3768 stat = RD32_IO_REG(ha, risc2host); in ql_reset_24xx_chip()
H A Dql_isr.c344 while (((stat = RD32_IO_REG(ha, risc2host)) & RH_RISC_INT) && in ql_isr_aif()
357 (RD32_IO_REG(ha, nx_risc_int) == 0 || in ql_isr_aif()
H A Dql_xioctl.c6035 (~(RD32_IO_REG(ha, gpiod))); in ql_blink_led()
6089 gpio_data = RD32_IO_REG(ha, gpiod); in ql_drive_led()
6094 gpio_data = RD32_IO_REG(ha, gpiod); in ql_drive_led()
6179 gpio_data = RD32_IO_REG(ha, gpiod); in ql_wrapup_led()
H A Dql_mbx.c103 RD32_IO_REG(ha, nx_host_int) & NX_MBX_CMD)) { in ql_mailbox_command()
/titanic_44/usr/src/uts/common/sys/fibre-channel/fca/qlc/
H A Dql_api.h229 #define RD32_IO_REG(ha, regname) \ macro
1904 RD32_IO_REG(ha, nx_risc_int) & NX_RISC_INT : \