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Searched refs:RADEON_WRITE (Results 1 – 4 of 4) sorted by relevance

/titanic_44/usr/src/uts/intel/io/drm/
H A Dradeon_cp.c874 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp); in radeon_do_pixcache_flush()
953 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0); in radeon_cp_load_microcode()
958 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, in radeon_cp_load_microcode()
960 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, in radeon_cp_load_microcode()
966 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, in radeon_cp_load_microcode()
968 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, in radeon_cp_load_microcode()
973 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, in radeon_cp_load_microcode()
975 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, in radeon_cp_load_microcode()
995 RADEON_WRITE(RADEON_CP_RB_WPTR, tmp); in radeon_do_cp_flush()
1024 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode); in radeon_do_cp_start()
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H A Dradeon_irq.c48 RADEON_WRITE(RADEON_GEN_INT_STATUS, irqs); in radeon_acknowledge_irqs()
289 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg); in radeon_enable_interrupt()
307 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); in radeon_driver_irq_preinstall()
338 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); in radeon_driver_irq_uninstall()
H A Dradeon_drv.h1008 #define RADEON_WRITE(reg, val) \ macro
1019 RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \
1026 RADEON_WRITE(RADEON_PCIE_DATA, (val)); \
1164 RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail); \
H A Dradeon_state.c2004 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * surf_index, in radeon_apply_surface_regs()
2006 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * surf_index, in radeon_apply_surface_regs()
2008 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * surf_index, in radeon_apply_surface_regs()