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Searched refs:PIPE_VBLANK_INTERRUPT_ENABLE (Results 1 – 2 of 2) sorted by relevance

/titanic_44/usr/src/uts/intel/io/drm/
H A Di915_irq.c528 PIPE_VBLANK_INTERRUPT_ENABLE); in i915_driver_irq_handler()
545 PIPE_VBLANK_INTERRUPT_ENABLE); in i915_driver_irq_handler()
809 PIPE_VBLANK_INTERRUPT_ENABLE); in i915_enable_vblank()
824 PIPE_VBLANK_INTERRUPT_ENABLE | in i915_disable_vblank()
H A Di915_drv.h771 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) macro