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Searched refs:PEU_INTR_MASK (Results 1 – 3 of 3) sorted by relevance

/titanic_44/usr/src/uts/common/io/hxge/
H A Dhxge_hw.c241 HXGE_REG_WR32(handle, PEU_INTR_MASK, 0xffffffff); in hxge_peu_handle_sys_errors()
H A Dhxge_virtual.c655 HXGE_REG_WR32(hxgep->hpi_handle, PEU_INTR_MASK, parity_err_mask.value); in hxge_ldgv_init()
H A Dhxge_peu_hw.h162 #define PEU_INTR_MASK (PIO_BASE_ADDR + 0x814C) macro