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Searched refs:MSR_AMD_GSBASE (Results 1 – 16 of 16) sorted by relevance

/titanic_44/usr/src/uts/i86pc/os/
H A Dmach_kdi.c166 old = (uintptr_t)rdmsr(MSR_AMD_GSBASE); in boot_kdi_tmpinit()
167 wrmsr(MSR_AMD_GSBASE, (uint64_t)cpu); in boot_kdi_tmpinit()
174 wrmsr(MSR_AMD_GSBASE, (uint64_t)old); in boot_kdi_tmpfini()
H A Dtrap.c1740 printf(fmt, "fsb", rdmsr(MSR_AMD_FSBASE), "gsb", rdmsr(MSR_AMD_GSBASE), in dumpregs()
/titanic_44/usr/src/grub/grub-0.97/stage2/
H A Dcontrolregs.h128 #define MSR_AMD_GSBASE 0xc0000101 /* 64-bit base address for %gs */ macro
/titanic_44/usr/src/uts/intel/sys/
H A Dcontrolregs.h184 #define MSR_AMD_GSBASE 0xc0000101 /* 64-bit base address for %gs */ macro
/titanic_44/usr/src/uts/intel/kdi/amd64/
H A Dkdi_asm.s89 movl $MSR_AMD_GSBASE, %ecx; \
99 movl $MSR_AMD_GSBASE, %ecx; \
329 movl $MSR_AMD_GSBASE, %ecx
/titanic_44/usr/src/uts/i86pc/ml/
H A Dbios_call_src.s142 movl $MSR_AMD_GSBASE, %ecx
429 movl $MSR_AMD_GSBASE, %ecx
H A Dfb_swtch_src.s134 movl $MSR_AMD_GSBASE, %ecx
H A Dmpcore.s279 movl $MSR_AMD_GSBASE, %ecx
H A Dcpr_wakecode.s149 movl $MSR_AMD_GSBASE, %ecx / save gsbase msr
708 movl $MSR_AMD_GSBASE, %ecx / restore gsbase msr
/titanic_44/usr/src/uts/intel/ia32/os/
H A Dsundep.c562 wrmsr(MSR_AMD_GSBASE, kgsbase); in update_sregs()
662 wrmsr(MSR_AMD_GSBASE, kgsbase); in reset_sregs()
H A Ddesctbls.c695 wrmsr(MSR_AMD_GSBASE, (uint64_t)&cpus[0]); in init_gdt()
H A Darchdep.c1088 PANICNVADD(pnv, "gsbase", rdmsr(MSR_AMD_GSBASE)); in panic_saveregs()
/titanic_44/usr/src/uts/intel/amd64/sys/
H A Dprivregs.h136 movl $MSR_AMD_GSBASE, %ecx; \
/titanic_44/usr/src/uts/i86xpv/os/
H A Dxpv_panic.c745 wrmsr(MSR_AMD_GSBASE, (uint64_t)&cpus[0]); in xpv_do_panic()
/titanic_44/usr/src/uts/intel/ia32/ml/
H A Dexception.s245 movl $MSR_AMD_GSBASE, %ecx; /* yes, set GSBASE */ \
/titanic_44/usr/src/uts/intel/dtrace/
H A Dfasttrap_isa.c1734 case REG_GSBASE: return (rdmsr(MSR_AMD_GSBASE)); in fasttrap_getreg()