Home
last modified time | relevance | path

Searched refs:MSR_AMD_EFER (Results 1 – 10 of 10) sorted by relevance

/titanic_44/usr/src/uts/i86pc/ml/
H A Dmpcore.s167 movl $MSR_AMD_EFER, %ecx
319 movl $MSR_AMD_EFER, %ecx
421 movl $MSR_AMD_EFER, %ecx
512 movl $MSR_AMD_EFER, %ecx
H A Dbios_call_src.s237 movl $MSR_AMD_EFER, %ecx /* Extended Feature Enable */
358 movl $MSR_AMD_EFER, %ecx
H A Dcpr_wakecode.s378 D16 movl $MSR_AMD_EFER, %ecx
667 movl $MSR_AMD_EFER, %ecx
1085 movl $MSR_AMD_EFER, %ecx
H A Dfb_swtch_src.s244 movl $MSR_AMD_EFER, %ecx /* Extended Feature Enable */
/titanic_44/usr/src/uts/i86pc/dboot/
H A Ddboot_grub.s246 movl $MSR_AMD_EFER, %ecx
263 movl $MSR_AMD_EFER, %ecx
/titanic_44/usr/src/grub/grub-0.97/stage2/
H A Dcontrolregs.h96 #define MSR_AMD_EFER 0xc0000080 /* extended feature enable MSR */ macro
H A Dexpand.c300 amd64_rdmsr(MSR_AMD_EFER, &efer); in amd64_config_cpu()
/titanic_44/usr/src/uts/intel/sys/
H A Dcontrolregs.h150 #define MSR_AMD_EFER 0xc0000080 /* extended feature enable MSR */ macro
/titanic_44/usr/src/uts/i86pc/os/
H A Dmp_startup.c2065 wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) | in cpu_asysc_enable()
2079 wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) & in cpu_asysc_disable()
/titanic_44/usr/src/uts/intel/ia32/ml/
H A Di86_subr.s3110 GETMSR(MSR_AMD_EFER, CREG_EFER, %rdi)