Searched refs:MSR (Results 1 – 7 of 7) sorted by relevance
42 #define MSR 6 /* ... modem status reg */ macro
123 latency threshold value to write into the MSR defined in MSRIndex (0x3F6). 140 This field maps to the Counter Mask (CMASK) field in IA32_PERFEVTSELx[31:24] MSR.143 This field corresponds to the Invert Counter Mask (INV) field in IA32_PERFEVTSELx[23] MSR.146 This field corresponds to the Any Thread (ANY) bit of IA32_PERFEVTSELx[21] MSR. 149 This field corresponds to the Edge Detect (E) bit of IA32_PERFEVTSELx[18] MSR.157 … the event uses the Precise Store feature and Bit 3 and bit 63 in IA32_PEBS_ENABLE MSR must be set
56 #define MSR 6 /* modem status register */ macro
1019 (INB(MSR) & DCD)) in asyopen()1421 (void) INB(MSR); in asy_program()1657 (void) INB(MSR); in asyintr()1981 msr = INB(MSR); /* this resets the interrupt */ in async_msint()2006 OUTB(MSR, (msr & 0xF0)); in async_msint()2102 val = INB(MSR) & 0xFF; in async_softint()3621 msr_r = INB(MSR); in asymctl()
65 #define MSR 6 /* modem status register */ macro
1655 asy->asy_msr = ddi_get8(asy->asy_iohandle, asy->asy_ioaddr + MSR); in asyopen()2068 asy->asy_ioaddr + MSR); in asy_program()2257 asy->asy_ioaddr + MSR); in asyintr()2572 msr = ddi_get8(asy->asy_iohandle, asy->asy_ioaddr + MSR); in async_msint()2613 msr = ddi_get8(asy->asy_iohandle, asy->asy_ioaddr + MSR); in async_msint()4286 asy->asy_ioaddr + MSR); in asymctl()
949 0328 K016: USB-MSR ISO 3-track MSR: POS Standard (See HID pages)950 0329 K018: USB-MSR JIS 2-Track MSR: POS Standard951 032a K016: USB-MSR ISO 3-Track MSR: HID Keyboard Mode952 032b K016/K018: USB-MSR Flash-Recovery/Download4354 4671 4820 LCD w/ MSR/KB