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Searched refs:MISC_REG_WC0_CTRL_MD_ST (Results 1 – 2 of 2) sorted by relevance

/titanic_44/usr/src/uts/common/io/bnxe/577xx/common/
H A Dbnxe_clc.c14759 REG_WR(cb, MISC_REG_WC0_CTRL_MD_ST, 0); in elink_warpcore_common_init()
/titanic_44/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A D57712_reg.h6268 #define MISC_REG_WC0_CTRL_MD_ST macro