Home
last modified time | relevance | path

Searched refs:MDIO_WC_REG_XGXSBLK1_LANECTRL1 (Results 1 – 2 of 2) sorted by relevance

/titanic_44/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A Dclc_reg.h543 #define MDIO_WC_REG_XGXSBLK1_LANECTRL1 0x8016 macro
/titanic_44/usr/src/uts/common/io/bnxe/577xx/common/
H A Dbnxe_clc.c4216 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16); in elink_warpcore_set_10G_KR()
4219 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16); in elink_warpcore_set_10G_KR()
4935 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16); in elink_warpcore_link_reset()
4944 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16); in elink_warpcore_link_reset()