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Searched refs:MDIO_WC_REG_TX0_ANA_CTRL0 (Results 1 – 2 of 2) sorted by relevance

/titanic_44/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A Dclc_reg.h547 #define MDIO_WC_REG_TX0_ANA_CTRL0 0x8061 macro
/titanic_44/usr/src/uts/common/io/bnxe/577xx/common/
H A Dbnxe_clc.c5128 MDIO_WC_REG_TX0_ANA_CTRL0, (1<<5)); in elink_warpcore_set_lane_polarity()