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Searched refs:MDIO_WC_REG_RX66_SCW1_MASK (Results 1 – 2 of 2) sorted by relevance

/titanic_44/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A Dclc_reg.h648 #define MDIO_WC_REG_RX66_SCW1_MASK 0x83c7 macro
/titanic_44/usr/src/uts/common/io/bnxe/577xx/common/
H A Dbnxe_clc.c4448 MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0); in elink_warpcore_set_20G_DXGXS()