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Searched refs:MDIO_WC_REG_RX1_PCI_CTRL (Results 1 – 2 of 2) sorted by relevance

/titanic_44/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A Dclc_reg.h564 #define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca macro
/titanic_44/usr/src/uts/common/io/bnxe/577xx/common/
H A Dbnxe_clc.c4140 MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane), in elink_warpcore_enable_AN_KR()
5118 MDIO_WC_REG_RX1_PCI_CTRL, (3<<2)); in elink_warpcore_set_lane_polarity()
5259 MDIO_WC_REG_RX1_PCI_CTRL, (1<<11)); in elink_warpcore_set_dual_mode()