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Searched refs:MDIO_REG_BANK_AER_BLOCK (Results 1 – 3 of 3) sorted by relevance

/titanic_44/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A Dphy_reg.h230 #define MDIO_REG_BANK_AER_BLOCK 0xFFD0 // Address Expansion Register macro
H A Dclc_reg.h257 #define MDIO_REG_BANK_AER_BLOCK 0xFFD0 macro
/titanic_44/usr/src/uts/common/io/bnxe/577xx/common/
H A Dbnxe_clc.c3596 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, in elink_set_aer_mmd()
4020 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, in elink_warpcore_restart_AN_KR()
4075 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, in elink_warpcore_enable_AN_KR()
4136 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, in elink_warpcore_enable_AN_KR()
4206 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, in elink_warpcore_set_10G_KR()
4371 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, in elink_warpcore_set_20G_force_KR2()
4409 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, in elink_warpcore_set_20G_force_KR2()
4915 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, in elink_warpcore_link_reset()
4966 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, in elink_set_warpcore_loopback()
5174 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, in elink_warpcore_set_quad_mode()
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