Searched refs:MDIO_AN_REG_CTRL (Results 1 – 2 of 2) sorted by relevance
| /titanic_44/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/ |
| H A D | clc_reg.h | 418 #define MDIO_AN_REG_CTRL 0x0000 macro
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| /titanic_44/usr/src/uts/common/io/bnxe/577xx/common/ |
| H A D | bnxe_clc.c | 4266 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0); in elink_warpcore_set_10G_XFI()
4383 MDIO_AN_REG_CTRL, 0); in elink_warpcore_set_20G_force_KR2()
4587 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0}, in elink_warpcore_clear_regs()
8052 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); in elink_807x_force_10G()
8253 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); in elink_8073_config_init()
9826 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); in elink_8706_config_init()
9982 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); in elink_8726_config_init()
10785 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, in elink_848xx_cmn_config_init()
11389 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); in elink_8481_link_reset()
12242 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val); in elink_7101_config_init()
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