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Searched refs:MC5_LRA_GMRREG_BASE_ADR0_2 (Results 1 – 1 of 1) sorted by relevance

/titanic_44/usr/src/uts/common/io/chxge/com/
H A Dmc5.c54 #define MC5_LRA_GMRREG_BASE_ADR0_2 0x00180060 macro
304 if (mc5_write(adap, MC5_LRA_GMRREG_BASE_ADR0_2 + i, in init_lara7000()