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Searched refs:L2 (Results 1 – 25 of 28) sorted by relevance

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/titanic_44/usr/src/lib/libast/common/uwin/
H A Dlog__L.c79 vc(L2, 3.9999999999970461961E-1 ,cccc,3fcc,2684,cccc, -1, .CCCCCCCCCC2684)
88 ic(L2, 3.9999999999416702146E-1, -2, 1.999999997FF24)
97 #define L2 vccast(L2) macro
110 return(z*(L1+z*(L2+z*(L3+z*(L4+z*(L5+z*(L6+z*(L7+z*L8))))))));
112 return(z*(L1+z*(L2+z*(L3+z*(L4+z*(L5+z*(L6+z*L7)))))));
/titanic_44/usr/src/lib/common/i386/
H A Dcrti.s82 call .L2
83 .L2: popl %ebx label
84 addl $_GLOBAL_OFFSET_TABLE_+[.-.L2], %ebx
/titanic_44/usr/src/lib/libc/amd64/gen/
H A Dmemchr.s63 jnz .L2 / goto .L2
93 .L2: label
101 jnz .L2 / goto .L2
H A Dstrcat.s70 .L2: label
79 je .L2 / goto .L2
87 jmp .L2 / goto .L2 (%rdi quadword aligned)
H A Dstrncat.s74 .L2: label
83 je .L2 / goto .L2
91 jmp .L2 / goto .L2 (%rdi quadword aligned)
/titanic_44/usr/src/lib/libc/i386/gen/
H A Dmemchr.s66 jnz .L2 / goto .L2
97 .L2: label
105 jnz .L2 / goto .L2
H A Dstrcat.s66 .L2: label
75 je .L2 / goto .L2
83 jmp .L2 / goto .L2 (%edi word aligned)
H A Dstrncat.s71 .L2: label
80 je .L2 / goto .L2
88 jmp .L2 / goto .L2 (%edi word aligned)
/titanic_44/usr/src/uts/i86pc/cpu/amd_opteron/
H A Dao_mca_disp.in44 desc = Correctable D$ data infill from L2$
76 desc = Uncorrectable D$ data infill from L2$
222 desc = L2 DTLB Parity Error
238 desc = L2 DTLB Parity Error (multimatch)
274 desc = Correctable I$ data infill from L2$
306 desc = Uncorrectable I$ data infill from L2$
404 desc = L2 ITLB Parity Error
420 desc = L2 ITLB Parity Error (multimatch)
458 desc = L2 data array single-bit ECC during TLB reload, snoop, or copyback
474 desc = L2 data array multi-bit ECC during TLB reload, snoop, or copyback
[all …]
/titanic_44/usr/src/uts/common/io/mac/
H A DREADME40 This is the kernel programming interface for accessing L2 services as
50 are used by L2 drivers to provide services to MAC consumers.
55 The GLDv3 L2 supports multiple types of media control. Each type is
/titanic_44/usr/src/uts/sun4u/serengeti/ml/
H A Dsbdp.il.cpp121 ! Panther needs to flush L2 before L3.
123 ! We need to free up a temp reg for the L2 flush macro (register usage
126 ! the L2 flush.
H A Dsbdp_asm.s169 ! Panther needs to flush L2 before L3 cache.
/titanic_44/usr/src/test/util-tests/tests/xargs/
H A Dxargs_test.ksh138 comp=$(printf "abc def\n123 456\npeterpiper" | $XARGS -L2 echo '**')
192 comp=$(printf "abc def \n123 456\npeter\nbogus" | $XARGS -L2 echo '**')
/titanic_44/usr/src/cmd/sgs/rtld.4.x/
H A Drtldlib.s49 L2: label
50 or %l7, %lo(__GLOBAL_OFFSET_TABLE_ - (L1 - L2)), %l7
/titanic_44/usr/src/uts/sparc/ml/
H A Dsparc.il54 ! prefetch 64 bytes into L2-cache
/titanic_44/usr/src/cmd/cmd-inet/usr.sbin/ipqosconf/
H A Dipqosconf.h43 #define L2 0x04 macro
H A Dipqosconf.c73 L2 |
3989 IPQOSCDBG0(L2, "In prepend_module_name\n"); in prepend_module_name()
/titanic_44/usr/src/uts/common/io/i40e/core/
H A Di40e_common.c613 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
614 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
615 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
618 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
619 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
622 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
623 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
624 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
625 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
626 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
[all …]
/titanic_44/usr/src/common/crypto/des/sun4u/
H A Ddes_crypt_asm.s2522 .L2: label
2611 ! bnz %icc, .L2
2702 ! bnz %icc, .L2
2793 ! bnz %icc, .L2
2884 ! bnz %icc, .L2
2975 ! bnz %icc, .L2
3066 ! bnz %icc, .L2
3157 ! bnz %icc, .L2
/titanic_44/usr/src/uts/intel/ia32/ml/
H A Dmodstubs.s195 jmp .L2
230 .L2: label
357 .L2: label
/titanic_44/usr/src/cmd/fm/eversholt/files/sparc/sun4v/
H A Dgcpu.esc55 * sun4v platforms. For example, one processor may have an L2
56 * cache per chip, another may have an L2 per core.
/titanic_44/usr/src/cmd/fm/dicts/
H A DSUN4V.po827 # code: SUN4V-8001-L2
830 msgid "SUN4V-8001-L2.type"
832 msgid "SUN4V-8001-L2.severity"
834 msgid "SUN4V-8001-L2.description"
836 msgid "SUN4V-8001-L2.response"
838 msgid "SUN4V-8001-L2.impact"
840 msgid "SUN4V-8001-L2.action"
H A DSCF.po261 msgstr "The number of correctable errors within a way of a CPU chip's L2 cache has exceeded an acce…
1957 msgstr "The number of correctable errors within the L2 cache tags of a SC chip has exceeded an acce…
1959 msgstr "One of the L2 cache ways is deconfigured for all the CPU chips associated with this SC chip…
2381 # code: SCF-8006-L2
2384 msgid "SCF-8006-L2.type"
2386 msgid "SCF-8006-L2.severity"
2388 msgid "SCF-8006-L2.description"
2390 msgid "SCF-8006-L2.response"
2392 msgid "SCF-8006-L2.impact"
2394 msgid "SCF-8006-L2.action"
[all …]
/titanic_44/usr/src/lib/libc/capabilities/sun4u-us3/common/
H A Dmemcpy.s810 ! of the L1 or L2 cache.
/titanic_44/usr/src/data/hwdata/
H A Dpci.ids21514 a009 PWRficient L2 Cache
21542 2048 Attansic L2 Fast Ethernet

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