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Searched refs:IXGBE_DCA_RXCTRL_DATA_WRO_EN (Results 1 – 4 of 4) sorted by relevance

/titanic_44/usr/src/uts/common/io/ixgbe/core/
H A Dixgbe_82598.c277 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | in ixgbe_start_hw_82598()
1376 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN | in ixgbe_enable_relaxed_ordering_82598()
H A Dixgbe_vf.c108 IXGBE_DCA_RXCTRL_DATA_WRO_EN | in ixgbe_virt_clr_reg()
H A Dixgbe_common.c443 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | in ixgbe_start_hw_gen2()
4332 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN | in ixgbe_enable_relaxed_ordering_gen2()
H A Dixgbe_type.h1372 #define IXGBE_DCA_RXCTRL_DATA_WRO_EN (1 << 13) /* Rx wr data Relax Order */ macro