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Searched refs:IXGBE_DCA_RXCTRL (Results 1 – 3 of 3) sorted by relevance

/titanic_44/usr/src/uts/common/io/ixgbe/core/
H A Dixgbe_82598.c276 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); in ixgbe_start_hw_82598()
279 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); in ixgbe_start_hw_82598()
1375 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); in ixgbe_enable_relaxed_ordering_82598()
1378 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); in ixgbe_enable_relaxed_ordering_82598()
H A Dixgbe_common.c442 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); in ixgbe_start_hw_gen2()
445 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); in ixgbe_start_hw_gen2()
4331 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); in ixgbe_enable_relaxed_ordering_gen2()
4334 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); in ixgbe_enable_relaxed_ordering_gen2()
H A Dixgbe_type.h344 #define IXGBE_DCA_RXCTRL(_i) (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \ macro