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Searched refs:INTEN0 (Results 1 – 2 of 2) sorted by relevance

/titanic_44/usr/src/uts/intel/io/amd8111s/
H A Damd8111s_hw.c267 WRITE_REG32(pLayerPointers, MemBaseAddress + INTEN0, 0x1F7F7F1F); in mdlClearHWConfig()
533 WRITE_REG32(pLayerPointers, pMdl->Mem_Address + INTEN0, in mdlHWReset()
541 WRITE_REG32(pLayerPointers, pMdl->Mem_Address + INTEN0, in mdlHWReset()
1686 WRITE_REG32(pLayerPointers, pMdl->Mem_Address + INTEN0, in SetIntrCoalesc()
H A Damd8111s_hw.h298 #define INTEN0 0x40 /* 32bit register */ macro