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Searched refs:IEEE1394_CSR_OFFSET_MASK (Results 1 – 5 of 5) sorted by relevance

/titanic_44/usr/src/uts/common/io/1394/
H A Ds1394_isoch.c353 (IEEE1394_SCSR_CHANS_AVAIL_HI & IEEE1394_CSR_OFFSET_MASK); in s1394_channel_alloc()
356 (IEEE1394_SCSR_CHANS_AVAIL_LO & IEEE1394_CSR_OFFSET_MASK); in s1394_channel_alloc()
559 (IEEE1394_SCSR_CHANS_AVAIL_HI & IEEE1394_CSR_OFFSET_MASK); in s1394_channel_free()
562 (IEEE1394_SCSR_CHANS_AVAIL_LO & IEEE1394_CSR_OFFSET_MASK); in s1394_channel_free()
749 IEEE1394_CSR_OFFSET_MASK), &old_value); in s1394_bandwidth_alloc()
779 IEEE1394_CSR_OFFSET_MASK), compare, swap, in s1394_bandwidth_alloc()
970 IEEE1394_CSR_OFFSET_MASK), &old_value); in s1394_bandwidth_free()
998 IEEE1394_CSR_OFFSET_MASK), compare, swap, in s1394_bandwidth_free()
H A Ds1394_csr.c557 offset = req->cmd_addr & IEEE1394_CSR_OFFSET_MASK; in s1394_CSR_state_clear()
670 offset = req->cmd_addr & IEEE1394_CSR_OFFSET_MASK; in s1394_CSR_state_set()
783 offset = req->cmd_addr & IEEE1394_CSR_OFFSET_MASK; in s1394_CSR_reset_start()
877 offset = req->cmd_addr & IEEE1394_CSR_OFFSET_MASK; in s1394_CSR_test_regs()
880 if ((offset == (IEEE1394_CSR_TEST_STATUS & IEEE1394_CSR_OFFSET_MASK)) && in s1394_CSR_test_regs()
973 offset = req->cmd_addr & IEEE1394_CSR_OFFSET_MASK; in s1394_CSR_cycle_time()
1056 offset = req->cmd_addr & IEEE1394_CSR_OFFSET_MASK; in s1394_CSR_bus_time()
1176 offset = (req->cmd_addr & IEEE1394_CSR_OFFSET_MASK); in s1394_CSR_IRM_regs()
1374 offset = (req->cmd_addr & IEEE1394_CSR_OFFSET_MASK); in s1394_common_CSR_routine()
H A Ds1394_misc.c976 offset = (IEEE1394_CSR_STATE_SET & IEEE1394_CSR_OFFSET_MASK); in s1394_cycle_too_long_callback()
H A Ds1394_dev_disc.c2356 IEEE1394_CSR_OFFSET_MASK), S1394_INVALID_NODE_NUM, in s1394_become_bus_mgr()
/titanic_44/usr/src/uts/common/sys/1394/
H A Dieee1394.h252 #define IEEE1394_CSR_OFFSET_MASK 0x00000000FFFF macro