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Searched refs:I915_GEM_DOMAIN_GTT (Results 1 – 2 of 2) sorted by relevance

/titanic_44/usr/src/uts/intel/io/drm/
H A Di915_gem.c47 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
386 if (write_domain & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) in i915_gem_set_domain_ioctl()
389 if (read_domains & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) in i915_gem_set_domain_ioctl()
410 if (read_domains & I915_GEM_DOMAIN_GTT) { in i915_gem_set_domain_ioctl()
958 I915_GEM_DOMAIN_GTT)) { in i915_gem_flush()
1302 ASSERT(!(obj->read_domains & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT))); in i915_gem_object_bind_to_gtt()
1303 ASSERT(!(obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT))); in i915_gem_object_bind_to_gtt()
1345 if (obj->write_domain != I915_GEM_DOMAIN_GTT) in i915_gem_object_flush_gtt_write_domain()
1396 obj->read_domains &= I915_GEM_DOMAIN_GTT; in i915_gem_object_set_to_gtt_domain()
1403 ASSERT(!((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0)); in i915_gem_object_set_to_gtt_domain()
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H A Di915_drm.h589 #define I915_GEM_DOMAIN_GTT 0x00000040 macro