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Searched refs:HC24_CLR_RISC_INT (Results 1 – 4 of 4) sorted by relevance

/titanic_44/usr/src/uts/common/io/fibre-channel/fca/qlc/
H A Dql_isr.c490 HC24_CLR_RISC_INT); in ql_isr_aif()
645 WRT32_IO_REG(ha, hccr, HC24_CLR_RISC_INT); in ql_spurious_intr()
707 WRT32_IO_REG(ha, hccr, HC24_CLR_RISC_INT); in ql_mbx_completion()
797 WRT32_IO_REG(ha, hccr, HC24_CLR_RISC_INT); in ql_async_event()
1420 WRT32_IO_REG(ha, hccr, HC24_CLR_RISC_INT); in ql_async_event()
1545 WRT32_IO_REG(ha, hccr, HC24_CLR_RISC_INT); in ql_response_pkt()
H A Dql_init.c3720 WRT32_IO_REG(ha, hccr, HC24_CLR_RISC_INT); in ql_reset_24xx_chip()
3727 WRT32_IO_REG(ha, hccr, HC24_CLR_RISC_INT); in ql_reset_24xx_chip()
3730 WRT32_IO_REG(ha, hccr, HC24_CLR_RISC_INT); in ql_reset_24xx_chip()
3764 WRT32_IO_REG(ha, hccr, HC24_CLR_RISC_INT); in ql_reset_24xx_chip()
3772 HC24_CLR_RISC_INT); in ql_reset_24xx_chip()
3775 WRT32_IO_REG(ha, hccr, HC24_CLR_RISC_INT); in ql_reset_24xx_chip()
H A Dql_api.c2269 WRT32_IO_REG(ha, hccr, HC24_CLR_RISC_INT); in ql_quiesce()
2277 HC24_CLR_RISC_INT); in ql_quiesce()
2280 WRT32_IO_REG(ha, hccr, HC24_CLR_RISC_INT); in ql_quiesce()
15101 HC24_CLR_RISC_INT); in ql_read_risc_ram()
15114 WRT32_IO_REG(ha, hccr, HC24_CLR_RISC_INT); in ql_read_risc_ram()
/titanic_44/usr/src/uts/common/sys/fibre-channel/fca/qlc/
H A Dql_api.h683 #define HC24_CLR_RISC_INT 0xA0000000 /* Clear RISC interrupt */ macro