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Searched refs:EMAC_REG_EMAC_MDIO_COMM (Results 1 – 3 of 3) sorted by relevance

/titanic_44/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/
H A Dlm_phy.c267 REG_WR(pdev,emac_base+EMAC_REG_EMAC_MDIO_COMM,tmp); in lm_mwrite()
274 tmp=REG_RD(pdev,emac_base+EMAC_REG_EMAC_MDIO_COMM); in lm_mwrite()
341 REG_WR(pdev,emac_base+EMAC_REG_EMAC_MDIO_COMM,val); in lm_mread()
347 val=REG_RD(pdev,emac_base+EMAC_REG_EMAC_MDIO_COMM); in lm_mread()
/titanic_44/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A Demac_reg_driver.h211 #define EMAC_REG_EMAC_MDIO_COMM 0xac //ACCESS:?? DataWidth:0x20 macro
/titanic_44/usr/src/uts/common/io/bnxe/577xx/common/
H A Dbnxe_clc.c2878 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); in elink_cl22_write()
2883 tmp = REG_RD(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); in elink_cl22_write()
2914 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); in elink_cl22_read()
2919 val = REG_RD(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); in elink_cl22_read()
2963 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); in elink_cl45_read()
2968 val = REG_RD(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); in elink_cl45_read()
2985 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); in elink_cl45_read()
2991 EMAC_REG_EMAC_MDIO_COMM); in elink_cl45_read()
3043 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); in elink_cl45_write()
3048 tmp = REG_RD(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); in elink_cl45_write()
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