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Searched refs:E1000_EICR_RX_QUEUE0 (Results 1 – 4 of 4) sorted by relevance

/titanic_44/usr/src/uts/common/io/e1000api/
H A De1000_defines.h581 #define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */ macro
636 #define E1000_EIMS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
653 #define E1000_EICS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
H A De1000_82575.h167 E1000_EICR_RX_QUEUE0 | \
/titanic_44/usr/src/uts/common/io/igb/
H A Digb_gld.c721 igb->eims_mask |= (E1000_EICR_RX_QUEUE0 << index); in igb_rx_ring_intr_enable()
749 igb->eims_mask &= ~(E1000_EICR_RX_QUEUE0 << index); in igb_rx_ring_intr_disable()
751 (E1000_EICR_RX_QUEUE0 << index)); in igb_rx_ring_intr_disable()
H A Digb_main.c4722 eims = (E1000_EICR_RX_QUEUE0 << i); in igb_setup_msix_82575()