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Searched refs:DBG_IB (Results 1 – 9 of 9) sorted by relevance

/titanic_44/usr/src/uts/sun4/io/px/
H A Dpx_ib.c60 DBG(DBG_IB, dip, "px_ib_attach\n"); in px_ib_attach()
99 DBG(DBG_IB, dip, "px_ib_detach\n"); in px_ib_detach()
124 DBG(DBG_IB, px_p->px_dip, in px_ib_intr_enable()
129 DBG(DBG_IB, px_p->px_dip, in px_ib_intr_enable()
150 DBG(DBG_IB, ib_p->ib_px_p->px_dip, "px_ib_intr_disable: ino=%x\n", ino); in px_ib_intr_disable()
155 DBG(DBG_IB, ib_p->ib_px_p->px_dip, in px_ib_intr_disable()
215 DBG(DBG_IB, dip, "px_ib_intr_dist_en: ino=0x%x\n", ino); in px_ib_intr_dist_en()
218 DBG(DBG_IB, dip, "px_ib_intr_dist_en: " in px_ib_intr_dist_en()
225 DBG(DBG_IB, dip, "px_ib_intr_dist_en: px_intr_getvalid() " in px_ib_intr_dist_en()
234 DBG(DBG_IB, dip, "px_ib_intr_dist_en: " in px_ib_intr_dist_en()
[all …]
H A Dpx_debug.h77 /* 32 */ DBG_IB, enumerator
H A Dpx_intr.c1001 DBG(DBG_IB, dip, in px_add_intx_intr()
/titanic_44/usr/src/uts/sun4u/io/pci/
H A Dpci_ib.c122 DEBUG0(DBG_IB, dip, "ib_destroy\n"); in ib_destroy()
163 DEBUG2(DBG_IB, pci_p->pci_dip, in ib_intr_enable()
869 DEBUG0(DBG_IB, ib_p->ib_pci_p->pci_dip, in ib_update_intr_state()
908 DEBUG1(DBG_IB, dip, "ib_get_intr_target: ino %x\n", ino); in ib_get_intr_target()
915 DEBUG1(DBG_IB, dip, "ib_get_intr_target: cpu_id %x\n", *cpu_id_p); in ib_get_intr_target()
939 DEBUG2(DBG_IB, dip, "ib_set_intr_target: ino %x cpu_id %x\n", in ib_set_intr_target()
947 DEBUG1(DBG_IB, dip, "ib_set_intr_target: orig mapreg value: 0x%llx\n", in ib_set_intr_target()
959 DEBUG0(DBG_IB, dip, "Clearing intr_enabled...\n"); in ib_set_intr_target()
965 DEBUG0(DBG_IB, dip, "About to check for pending interrupts...\n"); in ib_set_intr_target()
968 DEBUG0(DBG_IB, dip, "Waiting for pending ints to clear\n"); in ib_set_intr_target()
[all …]
H A Dpci_debug.c70 {DBG_IB, "ib"},
H A Dpcipsy.c530 DEBUG3(DBG_IB, dip, "pci_xlate_intr: bus=%x, dev=%x, intr=%x\n", in pci_xlate_intr()
535 DEBUG1(DBG_IB, dip, "pci_xlate_intr: done ino=%x\n", intr); in pci_xlate_intr()
/titanic_44/usr/src/uts/sun4u/sys/pci/
H A Dpci_debug.h76 #define DBG_IB (0x20ull << 32) macro
/titanic_44/usr/src/uts/sun4u/io/px/
H A Dpx_hlib.c296 DBG(DBG_IB, NULL, "hvio_ib_init - IMU_ERROR_LOG_ENABLE: 0x%llx\n", in hvio_ib_init()
299 DBG(DBG_IB, NULL, "hvio_ib_init - IMU_INTERRUPT_ENABLE: 0x%llx\n", in hvio_ib_init()
302 DBG(DBG_IB, NULL, "hvio_ib_init - IMU_INTERRUPT_STATUS: 0x%llx\n", in hvio_ib_init()
305 DBG(DBG_IB, NULL, "hvio_ib_init - IMU_ERROR_STATUS_CLEAR: 0x%llx\n", in hvio_ib_init()
2051 DBG(DBG_IB, NULL, "ino %x is invalid\n", devino); in hvio_intr_devino_to_sysino()
2250 DBG(DBG_IB, NULL, in hvio_msiq_init()
2257 DBG(DBG_IB, NULL, "hvio_msiq_init: " in hvio_msiq_init()
2413 DBG(DBG_IB, NULL, "hvio_msi_init: MSI_32_BIT_ADDRESS: 0x%llx\n", in hvio_msi_init()
2419 DBG(DBG_IB, NULL, "hvio_msi_init: MSI_64_BIT_ADDRESS: 0x%llx\n", in hvio_msi_init()
H A Dpx_lib4u.c2161 DBG(DBG_IB, pxp->px_dip, "px_cb_intr_redist: CB not enabled, " in px_cb_intr_redist()