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Searched refs:C_AFSR_CECC_ERRS (Results 1 – 3 of 3) sorted by relevance

/titanic_44/usr/src/uts/sun4u/sys/
H A Dus3_module.h55 #define C_AFSR_CECC_ERRS (C_AFSR_UMS | C_AFSR_IVPE | C_AFSR_CPC | \ macro
62 #define C_AFSR_CECC_ERRS (C_AFSR_UMS | C_AFSR_IVPE | C_AFSR_CPC | \
107 C_AFSR_CECC_ERRS | C_AFSR_ASYNC_ERRS | C_AFSR_ME)
151 #define C_AFSR_CECC_ERRS (C_AFSR_CE | C_AFSR_EMC | C_AFSR_EDU | \
170 C_AFSR_CECC_ERRS | C_AFSR_ASYNC_ERRS | C_AFSR_ME)
210 #define C_AFSR_CECC_ERRS (C_AFSR_CE | C_AFSR_EMC | C_AFSR_EDU | \
227 C_AFSR_CECC_ERRS | C_AFSR_ASYNC_ERRS | C_AFSR_ME)
H A Dcheetahregs.h1202 #define CPU_CE_NOT_DEFERRED (C_AFSR_CECC_ERRS & \
1206 #define CPU_CE_NOT_DEFERRED (C_AFSR_CECC_ERRS & \
1209 #define CPU_CE_NOT_DEFERRED (C_AFSR_CECC_ERRS & \
/titanic_44/usr/src/uts/sun4u/cpu/
H A Dus3_common.c6212 if (((cpu_error_regs.afsr & C_AFSR_CECC_ERRS) |
6449 (afsr_errs & (C_AFSR_CECC_ERRS | C_AFSR_EXT_CECC_ERRS)) == 0) {
7113 cpu_error_regs.afsr = C_AFSR_CECC_ERRS;